Specifications

3.4 DIO Status & Control Register (BASE + 18)

The data transfer mode of digital input is controlled and status is

checked through this register.

Address: BASE + 18

Attribute: READ/WRITE

Data Format:

Byte 7 6 5 4 3 2 1 0

Base +18

O_ACK DIN_EN I_TRG TRGPL I_FIFO I_TIME0 I_REQ I_ACK

Base +19

---- I_OVER ---- ---- O_TRG O_FIFO O_TIME1 O_REQ

Base +20

---- ---- ---- ---- ---- ---- ---- O_UND

Base +21

---- ---- ---- ---- ---- ---- ---- ----

♦♦ Digital Input Mode Setting:

I_ACK: Input ACK Enable

1: Input ACK is enabled (input ACK will be asserted after

input data is read by CPU or written to input FIFO)

0: Input ACK is disabled

I_REQ: Input REQ Strobe Enabled

1: Use I_REQ edge to latch input data

0: I_REQ is disabled

I_TIME0: Input Timer 0 Enable

1: Input is sampled by falling edge of Counter 0 output

(COUT0)

0: Input Timer 0 is disabled

I_FIFO: Input FIFO Enable Mode

1: Input FIFO is enabled (input data is saved to input

FIFO)

0: Input FIFO is disabled

TRGPOL: Input Trigger Polarity