User`s guide

Operation Theory
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37
scans of data. The process repeats until the specified amount of re-trigger
signals are detected. The total acquired data length = NumChan_counter *
PSC_counter * Retrig_no.
(NumChan _Counter=4, PSC_Counter=2, retrig_no=3)
A
cquisition_in_progress
Scan_start
A
D_conversion
Scan_in_progress
(SSHOUT)(pin8 on CN2)
A
cquired & stored data
(6 scans)
O
p
eration start
Trigger
Figure 20: Post trigger with retrigger
4.1.3.4 Bus-mastering DMA Data Transfer
PCI bus-mastering DMA is necessary for high speed DAQs in order to
utilize the maximum PCI bandwidth. The bus-mastering controller, which is
built in the PLX IOP-480 PCI controller, controls the PCI bus when it be-
comes the master of the bus. Bus mastering reduces the size of the
on-board memory and reduces the CPU loading because data is directly
transferred to the computer’s memory without host CPU intervention.
Bus-mastering DMA provides the fastest data transfer rate on PCI-bus.
Once the analog input operation starts, control returns to your program.
The hardware temporarily stores the acquired data in the on-board AD
Data FIFO and then transfers the data to a user-defined DMA buffer
memory in the computer. Please note that even when the acquired data
length is less than the Data FIFO, the AD data will not be kept in the Data
FIFO but directly transferred into host memory by the bus-mastering DMA.
The DMA transfer mode is very complex to program. We recommend using
a high-level program library to configure this card. If users would like to
know more about programs/software’s that can handle the DMA bus
master data transfer, please refer to http://www.plxtech.com for more in-
formation on PCI controllers.
By using a high-level programming library for high speed DMA data ac-
quisition, users simply need to assign the sampling period and the number