User`s guide

36
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Operation Theory
Delay Trigger Acquisition
Use delay trigger acquisition in applications to delay the data collecting
process after the occurrence of a specified trigger event. The delay time is
controlled by the value, which is pre-loaded in the
Delay_counter
(16bit).
The counter counts down on the rising edge of the Delay_counter clock
source after the trigger condition is met. The clock source is software
programmed and can be either the Timebase clock (40MHz) or the A/D
sampling clock (Timebase /SI2_counter). When the count reaches 0, the
counter stops and the board begins acquiring data. The total acquired data
length = NumChan_counter * PSC_counter.
(NumChan _Counter=4, PSC_Counter=3)
A
cquisition_in_progress
Scan_start
A
D_conversion
Scan_in_progress
(SSHOUT)(pin8 on CN2)
A
cquired & stored data
(3 scans)
O
p
eration start
Trigger
Delay until
Delay_Counter
reaches 0
Figure 19: Delay trigger
Note: When the Delay_counter clock source is set to Timebase, the
maximum delay time = 2
16
/40Ms = 1.638ms, and when set to A/D
sampling clock, the maximum delay time can be higher (2
16
*
SI2_counter/40M ).
Post-Trigger or Delay-trigger Acquisition with retrigger
Use post-trigger or delay-trigger acquisition with re-trigger function in ap-
plications where you want to collect data after several trigger events. The
number of scans after each trigger is specified in PSC_counter, and users
could program
Retrig_no
to specify the re-trigger numbers. Figure 20 il-
lustrates an example. In this example, 2 scans of data are acquired after
the first trigger signal, then the board waits for the re-trigger signal
(re-trigger signals which occur before the first 2 scans of data acquired will
be ignored). When the re-trigger signal occurs, the board scans 2 more