User`s guide

Operation Theory • 59
4.6 User-controllable Timing Signals
In order to meet the requirements for user-specific timing and the re-
quirements for synchronizing multiple cards, the DAQ/PXI-22XX series
provides flexible user-controllable timing signals to connect to external
circuitry or additional cards.
The whole DAQ timing of the DAQ/PXI-22XX series is composed of a
bunch of counters and trigger signals in the FPGA. These timing signals
are related to the A/D, D/A conversions and Timer/Counter applications.
These timing signals can be inputs to or outputs from the I/O connectors,
the SSI connector and the PXI bus. Therefore the internal timing signals
can be used to control external devices or circuitry’s.
We implemented signal multiplexers in the FPGA to individually choose the
desired timing signals for the DAQ operations, as shown in the figure 46.
Internal timing
signals
SSI timing
Signals
AFI timing
signals
DAQ timing
signals
SSI timing
Signals
Trigger_Out
timing signals
Figure 46: DAQ signals routing
Users can utilize the flexible timing signals through our software drivers,
and simply and correctly connect the signals with the DAQ/PXI-22XX se-
ries cards. Here is the summary of the DAQ timing signals and the corre-
sponding functionalities for DAQ/PXI-22XX series.
Timing signal category Corresponding functionality
SSI/PXI signals Multiple cards synchronization
AFI signals Control DAQ/PXI-22XX by external timing
signals
Figure 47: Summary of user-controllable timing signals and the
corresponding functionalities