User`s guide

48 • Operation Theory
4.6 Timer/Counter Operation
4.6.1 Introduction
One 8254 programmable interval timer/counter chip is integrated on the
PCI-9111. There are three counters available to the 8254 chip and 6 possible
operation modes for each counter. The block diagram of the timer/counter
system is shown in diagram below.
Counter #0
Internal 2 MHz Clock
Timer #1
Internal Timer Pacer
Timer #2
8254 Chip
G
C
G
C
G
O
O
O
'H'
'H'
AD Trigger Signal
Gate Control
Pre
-
Trigger
Control
Pre
-
Trigg
er
Signal
(Pin
-
12 of CN3)
C
Figure 16. Timer/Counter System of PCI-9111
4.6.2 Pacer Trigger Source
Timer #1 and Timer #2 are cascaded together to generate the timer pacer
trigger of the A/D conversion. The frequency of the pacer trigger is software
controllable. The maximum pacer signal rate is 2MHz/4=500K which excess
the maximum A/D conversion rate of the PCI-9111. The minimum signal rate is
2MHz/65535/65535, which is a very low frequency that users may never use.
The output of the programmable timer can be used as a pacer interrupt source
or a timer pacer trigger source for an A/D conversion. In the software library,
timer #1 and #2 are always set as mode 3 (rate generator).
4.6.3 Pre-Trigger Counter
Timer #0 is used as a pre-trigger counter. The clock source of counter 0 is from
the A/D trigger source so that the 8254 can count the A/D trigger numbers after
the pre-trigger signal (pin-12 of CN3) is inserted. The gate control is set when
the pre-trigger signal changes from ‘H’ to ‘L’, and is cleared when the counter
counts down to zero. In the software library, timer #0 is always set as mode 0
(event counter).