User`s guide

Operation Theory • 41
4.1.6 Post-Trigger Control
Another useful trigger mode is the Post-Trigger. Under “Post-Trigger” mode,
the post-trigger (POTRG) signal (from pin-12 of CN3) is used to “START” the
A/D sampling.
After setting up the Post-Trigger mode, the A/D converter will not acquire data
until the post-trigger signal is asserted. Users can poll the FIFO empty bit
(FF_EF) to detect whether the Post-Trigger signal is asserted or not. Once the
post-trigger is asserted, the hardware will begin to acquire data. Different from
Pre-Trigger control mode, user can acquire data continuously until the
Post-Trigger mode is disabled.
The following steps can be referenced for Post-Trigger control:
1. Disable all A/D trigger sources, ex: Timer-Pacer / Software trigger (TPST
= 0) and External / Internal trigger (EITS = 0). Set Post-Trigger mode ON:
POTRG = ON.
2. Set up A/D data acquire, including, A/D range, channel scan, data transfer
mode and so on.
3. Reset FIFO.
4. Enable the selected A/D trigger source (Timer-Pacer, Software or external
trigger).
5. Waiting for Post-Trigger signal assert. User can poll the FIFO empty bit to
see if the post-trigger signal starts or not.
6. Once post-trigger signal asserts, user starts to process data. To stop data
acquiring, disable the A/D trigger source.
7. Go to step 1 to start next Post-Trigger acquisition.