User`s guide

Operation Theory • 39
FIFO Half-Full Interrupt Transfer
Sometimes, the applications do not need real-time processing, but the
foreground program is too busy to poll the FIFO data, then the FIFO half-full
interrupt transfer mode is useful. In addition, as the external A/D trigger source
is used, the sampling rate may not be easy to predict, then the method could
be applied because the CPU only be interrupted when the FIFO is half-full,
thus reserved the CPU load.
Under this mode, an interrupt signal is generated when FIFO become half-full,
that means there are 512 word data in the FIFO already. The ISR can read a
block of data at every time an interrupt occurs. This method is very convenient
to reading the A/D in size of a “block” (512 words) and it benefits software
programming.
4.1.5 Pre-Trigger Control
In certain applications, the data acquisition is applied and stops under special
hardware signal. Without Pre-Trigger function, the software can start the A/D
at any time, but it is very difficult to stop the A/D in real-time by software. Under
“Pre-Trigger” mode, the pre-trigger (PTRG) signal (from pin-12 of CN3) and
the 8254 counter 0 are used to “STOP” the A/D sampling.
After setting up the Pre-Trigger mode, the hardware is continuously acquiring
A/D data and waiting for the pre-trigger signal. Before the pre-trigger signal is
inserted, the software must read the FIFO data to prevent FIFO full. Besides, if
these data are usable, the software should store these data as many as
possible to the host PC‘s memory.
When the pre-trigger signal is inserted, the counter starts to count down from
the initial counter value N to count the number of the A/D conversion trigger
signal. The A/D trigger will be disabled automatically when the counter value
reaches zero. The value of N could be 1 to 65535 and the last N A/D data is
sampled after the pre-trigger signal. The software must continuously read data
out from the FIFO to prevent the FIFO being full. The software also should poll
the counter value to check if the A/D sampling is stopped.