User`s guide

36 • Operation Theory
Signal Range
A properly define signal range is important in any data acquisition process. The
input signal may be saturated if the A/D gain is too large or the resolution may
be not enough if the signal is small. The maximum A/D signal range of the
PCI-9111 is +/- 10 volts when the A/D gain value is 1. The A/D gain control
register controls the maximum signal input range. The signal gain is
programmable with 5 levels (1, 2, 4, 8, 16). The signal ranges of the 16
channels are identical at all times.
The available signal polarity on PCI-9111 is bi-polar. However, the bi-polar
input range can still cover a uni-polar application. In addition the high
resolution of the PCI-9111HR can cover most applications.
4.1.3 A/D Trigger Source Control
An A/D conversion is started when a trigger signal is detected. With the
PCI-9111, an A/D conversion can be triggered by either an Internal or External
trigger source. The EITS bit of the A/D control register is used to handle an
internal or external trigger. Refer to section 3.9 for details. Whenever an
external source is set, the internal sources are disabled.
If an internal trigger is selected, two internal sources can be selected, either
software or timer pacer trigger. The A/D bits EITS and TPST of the A/D mode
register controls the A/D operations mode. There are 3 different trigger
conditions available to the PCI-9111. The different trigger conditions are
specified below:
Software trigger (EITS=0, TPST=0)
The trigger source is software controllable in this mode. That is, the A/D
conversion is started when any value is written into the software trigger register.
This trigger mode is suitable for low speed A/D conversions. Under this mode,
the timing of the A/D conversion is fully controlled by the software. However, it
is difficult to control a fixed A/D conversion rate unless another timer interrupt
service routine is used to generate a fixed rate trigger. Refer to the interrupt
control section for fixed rate timer interrupt.
Timer Pacer Trigger (EITS=0, TPST=1)
The on-board timer/counter chip 8254 is used to provide a trigger source for an
A/D conversion at a fixed rate. Two counters of the 8254 chip are cascaded
together to generate a trigger pulse at precise periods. Refer to section 4.6 for
timer/counter operations. This mode is ideal for high speed A/D conversion. It
can be combined with the FIFO half full interrupt or EOC interrupt to transfer
data. The A/D trigger, A/D data transfer and Interrupt can be set independently,
thus most complex applications can be covered.