User`s guide

Registers • 29
3.13 ISC2 & Trigger Event Read Back Register
The interrupt control setting ISC2 and the trigger event can be retrieved from
this register. Refer to section 3.9 and section 3.10 for details of each bit.
Address: BASE + 0Ch
Attribute: read only
Data Format:
Bit 7 6 5 4 3 2 1 0
BASE+0Ah X X X X X X TRGEVENT ISC2
BASE+0Bh X X X X X X X X
ISC2: IRQ2 select bit, refer to section 3.10 for detail.
TRGEVENT: pre-trigger and post-trigger event.
1: trigger event occurs
0: trigger event not occurs