User`s guide

28 • Registers
3.11 Hardware Interrupt Clear Register
Becaus e the PCI interrupt signal is level triggered, the interrupt clear register
must be written to in order to clear the flag after processing an interrupt request
event, otherwise another interrupt request will be inserted and will cause the
software to hang on processing the interrupt event.
Address: BASE + 48h
Attribute: write only
Data Format:
Bit 7 6 5 4 3 2 1 0
BASE+48h X X X X X X X X
3.12 A/D Mode & Interrupt Control Read Back Register
The AD mode setting and interrupt control setting can be read from this
register. Refer to section 3.9 and section 3.10 for detail definition of each bit.
Address: BASE + 0Ah
Attribute: read only
Data Format:
Bit 7 6 5 4 3 2 1 0
BASE+0Ah POTRG FFEN ISC1 ISC0 PTRG EITS TPST ASCAN
BASE+0Bh X X X X X X X X