User`s guide

Registers • 27
Note 1: The bits in this register can only control the A/D trigger source and
trigger method. The trigger conditions are independent from data
transfer method and interrupt generation.
Note 2: The setting of Pre-trigger and Post-trigger in bit 3 & 4 are exclusive.
There is only one mode can be enabled at one time
Note 3: TRGEVENT and POTRG bits support for hardware revision B2. It’s not
available in old version.
3.10 Interrupt Control Register
The PCI-9111 has a dual interrupt system, thus two interrupt sources can be
generated and can be checked using the software. This register is used to
select the interrupt source.
Address: BASE + 0Ch
Attribute: write only
Data Format:
Bit 7 6 5 4 3 2 1 0
BASE+0Ch X X X X ISC2 FFEN ISC1 ISC0
ISC0: IRQ0 signal select
0: IRQ on the ending of the AD conversion (EOC)
1: IRQ when FIFO is half full
ISC2 ISC1 IRQ1 signal select
0 0 IRQ every Timer tick
0 1 IRQ when ExtTrg signal changes from ‘H’ to ‘L’
1 0 IRQ when pre-trigger counter is counting down to 0
FFEN: FIFO enable pin
0: FIFO Enable (Power On Default value)
1: FIFO Disable
(To reset the FIFO, set FFEN sequence as 0 -> 1 -> 0)
Note 1: ISC2 control bit is only supported with hardware version B2, i.e. An
IRQ is available when the pre-trigger counter is counting down.