User`s guide

26 • Registers
3.9 A/D Trigger Mode Control Register
This register is used to control the A/D trigger source and trigger method.
Address: BASE + 0Ah
Attribute: write only
Data Format:
Bit 7 6 5 4 3 2 1 0
BASE+0Ah X X TRGEVENT POTRG PTRG EITS TPST
ASCAN
BASE+0Bh X X X X X X X X
TRGEVENT: Post / Pre-rigger event flag clear, write 1 to clear the trigger event
POTRG: Post-trigger ON/OFF control
0: Post-trigger OFF
1: Post-Trigger ON
PTRG: Pre-trigger ON/OFF control
0: Pre-trigger OFF
1: Pre-Trigger ON
EITS: External / Internal Trigger Source
1: External Trigger Source
0: Internal Trigger Source
TPST: Timer Pacer/ Software Trigger
0: Software Trigger
1: Timer Pacer Trigger
ASCAN: Auto Scan Control
0: Auto Scan OFF
1: Auto Scan ON
Only the modes listed below applied on the PCI-9111 card:
Bit 4
POTRG
(Note 2)
Bit 3
PTRG
Bit 2
EITS
Bit 1
TPST
Bit 0
ASCAN
Mode Description (Note 1)
0/1 0/1 0 0 0/1 Software Trigger & Polling
0/1 0/1 0 1 0/1 Timer Pacer Trigger
0/1 0/1 1 X 0/1 External Trigger