NuDAQ-2500 Series High Performance Analog Output and Multi-function Data Acquisition Cards User’s Manual Manual Rev. 2.01 Revision Date: March 19, 2006 Part No: 50-11221-2000 Advance Technologies; Automate the World.
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Using this manual 1.1 Audience and scope This manual guides you when using ADLINK NuDAQ-2500 Series card. The card’s hardware, signal connections, and calibration information are provided for faster application building. This manual is intended for computer programmers and hardware engineers with advanced knowledge of data acquisition and high-level programming. 1.
1.3 Conventions Take note of the following conventions used throughout the manual to make sure that you perform certain tasks and instructions properly. NOTE Additional information, aids, and tips that help you perform particular tasks. IMPORTANT Critical information and instructions that you MUST perform to complete a task. WARNING Information that prevents physical injury, data loss, module damage, program corruption etc. when trying to complete a particular task.
Table of Contents Table of Contents..................................................................... i List of Tables.......................................................................... iii List of Figures ........................................................................ iv 1 Introduction ........................................................................ 1 1.1 1.2 1.3 1.4 1.5 Features............................................................................... 1 Applications .....
3 Signal Connections .......................................................... 17 3.1 Connectors Pin Assignment............................................... 17 4 Operation Theory .............................................................. 21 4.1 4.2 4.3 4.4 4.5 4.6 A/D Conversion.................................................................. 21 AD Data Format ............................................................ 22 Acquisition Modes ......................................................
List of Tables Table 3-1: VHDCI-type (68-pin) Connector Pin Assignment ... Table 3-2: VHDCI-type (68-pin) Connector Legend ................ Table 4-1: Bipolar Input Range and Converted Digital Codes ......................................... Table 4-2: Unipolar Input Range and Converted Digital Codes ......................................... Table 4-3: Trigger Modes and Corresponding Trigger Sources ............................. Table 4-4: Summary of Counters for Programmable Scan ......
List of Figures Figure 1-1: DAQ-/DAQe-/PXI-2502/2501 Block Diagram ............ 7 Figure 2-1: DAQe-2502/2501 Card Layout ................................ 13 Figure 2-2: DAQ-2502/2501 Card Layout .................................. 14 Figure 2-3: DAQ-2502/2501 Card Layout .................................. 15 Figure 4-1: Scan Timing............................................................. 25 Figure 4-2: Post Trigger .............................................................
1 Introduction The NuDAQ-2500 Series features the DAQ-/DAQe-/PXI-2502/ 2501 advanced analog output card based on the 32-bit PCI/PCI Express®/PXI architecture. With high-performance designs and state-of-the-art technology, these cards are ideal for waveform generation, industrial process control, and signal analysis applications in medical, process control, etc. 1.
X System Synchronization Interface (SSI) X A/D and D/A fully auto-calibration X Built-in programmable D/A external reference voltage compensator X Jumper-less operation and software-configurable 1.
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Analog Input (AI) X Z DAQ-/PXI-2502: 4 single-ended Z DAQ-/PXI-2501: 8 single-ended X AD converter: LTC1416 X Max sampling rate: 400 KS/s X Resolution: 14-bit X FIFO buffer size: 2K samples X Input range Z Bipolar: ±10 V Z Unipolar: 0 V to 10 V X Over-voltage protection: Continuous, ±35 V maximum X Input impedance: 1 GΩ / 6 pF X Trigger modes: Pre-trigger, post-trigger, middle-trigger, and delay trigger X Data transfers: Programmed I/O and bus-mastering DMA with scatter/gather X I
General Purpose Digital I/O (G. P. DIO) X Channels: 24 programmable input/output X Compatibility: TTL/CMOS X Input voltage: X Z Logic Low: VIL=0.8 V max; IIL=0.2 mA max Z High: VIH=2.0 V max; IIH=0.02 mA max Output voltage: Z Low: VOL=0.5 V max; IOL=8 mA max Z High: VOH=2.
System Synchronous Interface (SSI) X Trigger lines: 7 Calibration X Recommended warm-up time: 15 minutes X Onboard reference: 5.0 V X Temperature coefficient: ±2 ppm/°C X Long-term stability: 6 ppm/1000 hr Physical X Dimension: 175 mm by 107 mm X I/O connector: 68-pin female mini-SCSI type X Power Requirement: +5 VDC; 1.
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1.5 Software Support ADLINK provides versatile software drivers and packages for users’ different approach to building up a system. ADLINK not only provides pro-gramming libraries such as DLL for most Windowsbased systems, but also provide drivers for other software packages such as LabVIEW®. All software options are included in the ADLINK CD. Non-free software drivers are protected with licensing codes.
DAQ-LVIEW PnP: LabVIEW Driver DAQ-LVIEW PnP contains the VIs, which are used to interface with NI’s LabVIEW software package. The DAQ-LVIEW PnP supports Windows 98/NT/2000/XP. The LabVIEW drivers is shipped free with the card. You can install and use them without a license. For detailed information about DAQ-LVIEW PnP, refer to the user’s guide in the CD.
10 Introduction
2 Installation This chapter describes how to install the DAQ-/DAQe-/PXI-2502/ 2501 card. The contents of the package and unpacking information that you should be aware of are outlined first. The DAQ-/DAQe-/PXI-2502/2501 card performs an automatic configuration of the IRQ and port address. You can use the PCI_SCAN software utility to read the system configuration. 2.
2.2 Unpacking Your DAQ-/DAQe-/PXI-2502/2501 card contains electro-static sensitive components that can be easily be damaged by static electricity. Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat. Inspect the card package for obvious damages. Shipping and handling may cause damage to the card.
2.
DAQ-2502/2501 Figure 2-2: DAQ-2502/2501 Card Layout 14 Installation
DPXI-2501/2502 Figure 2-3: DAQ-2502/2501 Card Layout Installation 15
2.4 PCI Configuration Plug and Play With support for plug and play, the card requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load seen by the system. Configuration The board configuration is done on a board-by-board basis for all PCI boards in the system.
3 Signal Connections This chapter describes DAQ-/DAQe-/PXI-2502/2501 card connectors and the signal connection between the DAQ-/DAQe-/PXI2502/2501 card and external devices. 3.1 Connectors Pin Assignment The DAQ-/DAQe-/PXI-2502/2501 card is equipped with two 68-pin VHDCI-type connectors (AMP-787254-1). These are used for digital input/output, analog input/output, timer/counter signals, etc. The pin assignments of the connectors are defined in Table 3-1.
AO_0 AO_1 AO_2 AO_3 AOEXTREF_A/AI_0 AI_1 EXTATRIG/AI_2 AOEXTREF_B/AI_3 AO_4/AI_4 AO_5/AI_5 AO_6/AI_6 AO_7/AI_7 AO_TRIG_OUTA AO_TRIG_OUTB GPTC1_SRC GPTC0_SRC GPTC0_GATE GPTC0_OUT GPTC0_UPDOWN RESERVED AFI1 PB7 PB5 PB3 PB1 PC7 PC5 DGND PC3 PC1 PA7 PA5 PA3 PA1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND A
Legend: Pin # Signal Name Reference Direction Description Voltage output of DA channel <0..3> 1~4 AO_<0..3> AGND Output 5 AOEXTREF_A/AI_0 AGND Input External reference for AO channel <0..3> / AI input 2 6 AI_1 AGND Input AI input 0 7 EXTATRIG/AI_2 AGND Input External analog trigger / AI input 1 8 AOEXTREF_B/AI_3 AGND Input External reference for AO channel <4..7> / AI input 3 9~12 AO_<4..7>/AI_<4..7> AGND Output/Input Voltage output of DA channel <4..7> / AI channel <4..
20 Signal Connections
4 Operation Theory The operation theories of the DAQ-/DAQe-/PXI-2502/2501 card are described in this chapter. The functions include A/D conversion, D/A conversion, digital I/O, and general purpose counter/ timer. This operation theory will help you understand how to configure and program the DAQ-/DAQe-/PXI-2502/2501 card. 4.1 A/D Conversion When using an A/D converter, you must know about the properties of the signal to be measured.
AD Data Format The data format of the acquired 14-bit A/D data is coded in 2’s complement. Table 4-1 and Table 4-2 lists the valid input ranges and the ideal transfer characteristics. Magnitude FSR LSB FSR-1LSB Bipolar Input Range ±10V ±5V ±2.5V ±1.25V 1120.78uV 610.39uV 305.19uV 152.60uV 9.998779V 4.999389V 2.499694V 1.249847V Midscale + LSB 1120.78uV Midscale 0V -10V 1FFF 610.39uV 305.19uV 152.60uV 0001 0V 0V 0V 0000 -305.19uV -152.60uV 3FFF -2.5V -1.
Acquisition Modes Software Polling This is the easiest way to acquire a single A/D data. The A/D converter starts one conversion whenever the dedicated software command is executed. Then the software would poll the conversion status and read the A/D data back when it is available. This method is very suitable for applications that needs to process A/D data in real time. Under this mode, the timing of the A/D conversion is fully controlled by the software.
Scan Timing and Procedure There are four counters that need to be specified prior to programmable scans. Refer to Table 4-4 for details. Counter Name Width Description Notes SI_counter Scan Interval defines the 24-bit interval between each scan. Scan Interval = SI_counter / Time-base* SI2_counter Sampling Interval defines 24-bit the interval between each sampled channel.
The relationship between counters and acquisition timing is illustrated in Figure 4-1. Figure 4-1: Scan Timing NOTE The maximum A/D sampling rate is 400 KHz for DAQ-/ DAQe-/PXI-2502/2501 card. The minimum setting of SI2_counter is 100. The Scan Interval may not be smaller than the interval of data Sampling Interval multiplied by the Number of channels per Scan. For example: SI_counter >= SI2_counter * NumChan_Counter.
Trigger Modes Post-Trigger Acquisition Use post-trigger acquisition when you want to perform scans right after a trigger signal. The number of scans to be performed after the trigger signal is specified by the PSC_counter, as illustrated in Figure 4-2.
Delay Trigger Acquisition Use delay trigger when you want to delay the scan after a trigger signal. The delay time is determined by the Delay_counter, as shown in Figure 4-3. The counter counts down on the rising edges of Delay_counter clock source after the trigger signal. When the count reaches 0, the DAQ-/DAQe-/PXI-2502/2501 card starts to perform the scan.
Post-Trigger or Delay-trigger Acquisition with Retrigger Use post-trigger or delay-trigger acquisition with retrigger when you want to perform repeated scans with respect to the repeated triggers. Figure 4-4 illustrates this mode. Two scans are performed after the first trigger signal, and then waits for the next trigger signal. When the trigger signal occurs, it performs two more scans. When retrigger function is disabled, only one trigger signal is be accepted after retrigger.
Bus-mastering DMA Data Transfer Bus Mastering DMA Mode PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum PCI bandwidth. The bus-mastering controller, which is built in the PLX PCI controller, controls the PCI bus when it becomes the master of the bus. Bus mastering reduces the required size of the onboard memory and reduces the CPU loading because data is directly transferred to the computer’s memory without host CPU intervention.
gather function, including some sample programs in the ADLINK All-in-One CD.
4.2 D/A Conversion The DAQ-/DAQe-/PXI-2502/2501 card offers flexible and versatile analog output scheme to fit your complex field applications. In order to take full advantages of the DAQ-/DAQe-/PXI-2502/2501 card, it is suggested that you carefully read this section. Architecture There are up to eight channels of 12-bit Digital-to-Analog Converter (DAC) available in the DAQ-/DAQe-/PXI-2502/2501 card. Four D/A channels are packed into one D/A group.
Hardware-Controlled Waveform Generation FIFO is a hardware first-in first-out data queue that holds temporary digital codes for D/A conversion. When the DAQ-/DAQe-/PXI2502/2501 card operates in waveform generation mode, the waveform patterns are stored in FIFO with 8K maximum samples. Waveform patterns larger than 8K are also supported by utilizing bus-mastering DMA transfer supported by the PCI controller. The data format in FIFO is shown in Figure 4-7.
Data Format in FIFO and Mapping With hardware-based waveform generation, D/A conversions are updated automatically by CPLD rather than application software. Unlike the conventional software-based waveform generation, the precise hardware timing control guarantees non-distorted waveform generation even when host CPU is under heavy loading. Detailed function setup are discussed later on this chapter.
Using DACs’ Multiplying Characteristic The D/A reference selection let you fully utilize the multiplying characteristics of the DACs. Digital codes sent to the D/A converters are multiplied by the reference to generate output.
Waveform Generation This method is suitable for applications that need to generate waveforms at a precise and fixed rate. Various programmable counters will facilitate users to generate complex waveforms with great flexibility. Three event signals are involved in waveform generation: Start, DAWR (DA WRite), and Stop. Refer to Table 4-6 for a brief summary of waveform generation events and their corresponding trigger sources.
Waveform Generation Timing Six counters interact with the waveform to generate different DAWR timing, thus forming different waveforms. These are described in Table 4-7. Counter Name Width Description Note UI_counter Update Interval, which defines the update inter24-bit val between each data output. UC_counter Update Counts, which 24-bit defines the number of data in a waveform. IC_counter Iteration Counts, which defines how many times 16-bit the waveform is generated.
Figure 4-8: Typical D/A Timing of Waveform Generation (Assuming the data in the data buffer are 2V, 4V, -4V, 0V) Operation Theory 37
Trigger Modes Post-Trigger Generation Use post-trigger generation when you want to generate waveform right after a trigger signal. The number of patterns to be updated after the trigger signal is specified by UC_counter* IC_counter, as illustrated in Figure 4-9.
Delay-Trigger Generation Use delay-trigger when you want to delay the waveform generation after the trigger signal. The delay time is determined by DLY1_counter as shown in Figure 4-10. The counter counts down on the rising edges of DLY1_counter clock source after the start trigger signal. When the count reaches zero, the DAQ-/DAQe-/PXI-2502/2501 card starts to generate the waveform.
Post-Trigger or Delay-Trigger with Retrigger Use post-trigger or delay-trigger with retrigger when you want to generate multiple waveforms with respect to multiple incoming trigger signals. You can set Trig_counter to specify the number of acceptable trigger signals. Figure 4-11 illustrates this example with an Iterative Waveform Generation. Refer to next section for details. Two waveforms are generated after the first trigger signal. The board then waits for another trigger signal.
Iterative Waveform Generation You can set the IC_counter to generate iterative waveforms, no matter which trigger mode is used. The IC_counter stores the iteration number. Examples shown in Figure 4-12 and Figure 4-13 assumes that the digital codes in the FIFO are 2V, 4V, 2V, and 0V.
When IC_counter is disabled, the waveform generation does not stop until a stop trigger is asserted. For Stop Mode, refer to the next section. An onboard data FIFO is used to buffer the waveform patterns for waveform generation. If the size of a single waveform is smaller than that of the FIFO, after initially loading the data from the host memory, the data in FIFO is re-used when a single waveform generation is completed. It does not occupy the PCI bandwidth afterwards.
Stop Modes You may stop waveform generation while it is still in progress, either by hardware or software trigger. The stop trigger sources can be software selected from internal software trigger, external digital trigger (AFI-0/1), or analog trigger. Three stop modes are provided to stop finite or infinite waveform generation. Stop Mode I After a mode I stop trigger is asserted, the waveform generation stops immediately. Figure 4-14 illustrates this example.
Figure 4-15: Stop Mode II Stop Mode III After a mode III stop trigger is asserted, the waveform generation continues until the iterative number of waveforms specified in IC_Counter is completed. Figure 4-16 is shown as an example. Since IC_Counter is set to three, the total generated waveforms must be a multiple of three. You can check WFG_in_progress (waveform generation in progress) status by software read-back to confirm the stop of a waveform generation.
4.3 General Purpose Digital I/O The DAQ-/DAQe-/PXI-2502/2501 card provides a 24-line generalpurpose digital I/O (GPIO) via the 82C55A chip. The 24-line GPIO are separated into three ports: Port A, Port B and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of each port can be individually programmed to be either inputs or outputs. Upon system startup or reset, all GPIO pins are reset to high impedance inputs. For more information on 82C55A programmable I/O chip, visit http://www.intel.com.
4.4 General Purpose Timer/Counter Operation Two independent 16-bit up/down timer/counter are embedded in FPGA firmware for user applications.
General Purpose Timer/Counter Modes Eight programmable timer/counter modes are provided. All modes start operations following the software start command. The GPTC software reset command initializes the status of the counter and re-loads the initial value to the counter. Mode1: Simple Gated-Event Counting The counter counts the number of pulses on the GPTC_CLK after the software start. Initial count value can be loaded via software. Current count value can be read-back by software at anytime.
Figure 4-18: Mode2 Operation Mode3: Single Pulse-width Measurement The counter counts the pulse-width of the signal on GPTC_GATE in terms of GPTC_CLK. Initial count can be loaded via software. After the software start, the counter counts the number of active edges on GPTC_CLK when GPTC_GATE is active. GPTC_OUT outputs high, and current count value can be read-back via software after the completion of the pulse-width measurement.
Mode4: Single Gated Pulse Generation This mode generates a single pulse with programmable delay and programmable pulse-width following the software start. These software programmable parameters could be specified in terms of periods of the GPTC_CLK. GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the counting. Figure 4-20 illustrates the generation of a single pulse with pulse-delay of two and pulse-width of four.
Mode6: Re-triggered Single Pulse Generation This mode is similar to mode 5 except that the counter generates a pulse following every active edge on GPTC_GATE. After the software start, every active GPTC_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC_GATE trigger that occurs during the pulse generation is ignored. Figure 4-22 illustrates the generation of two pulses with pulse delay of two and pulse-width of four.
Mode8: Continuous Gated Pulse Generation This mode generates periodic pulses with programmable pulse interval and pulse-width following the software start. GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the current count value. Figure 4-24 illustrates the generation of two pulses with pulse delay of four and pulse-width of three.
4.5 Trigger Sources The DAQ-/DAQe-/PXI-2502/2501 card provides flexible trigger selections. In addition to software trigger, the DAQ-/DAQe-/PXI2502/2501 card also supports external analog and digital triggers. You can configure the trigger source for A/D and D/A processes individually via software. NOTE A/D and D/A conversions share the same analog trigger. Software-Trigger This trigger mode does not need any external trigger source. The trigger asserts right after you execute the specified function call.
Trigger Level digital setting Trigger voltage 0xFF 9.92V 0xFE 9.84V --- --- 0x81 0.08V 0x80 0 0x7F -0.08V --- --- 0x01 -9.92V 0x00 -10V Table 4-8: Ideal Transfer Characteristic of Analog Trigger SRC1 (EXTATRIG) The trigger signal asserts when an analog trigger condition is met. There are five analog trigger conditions in DAQ-/DAQe-/PXI-2502/ 2501 card.
Above-High Analog Trigger Condition Figure 4-27 shows the above-high analog trigger condition, the trigger signal asserts when the input analog signal is higher than the High_Threshold voltage. The Low_Threshold setting is not used in this trigger condition.
High-Hysteresis Analog Trigger Condition Figure 4-29 shows the high-hysteresis analog trigger condition. The trigger signal asserts when the input analog signal level is higher than the High_Threshold voltage, where the hysteresis region is determined by the Low_Threshold voltage. Figure 4-29: High-Hysteresis Analog Trigger Condition Low-Hysteresis Analog trigger condition Figure 4-30 shows the low-hysteresis analog trigger condition.
4.6 Timing Signals In order to meet the requirements for user-specific timing or synchronizing multiple boards, the DAQ-/DAQe-/PXI-2502/2501 card provides a flexible interface for connecting timing signals with external circuitry or other boards. The DAQ timing of the DAQ-/ DAQe-/PXI-2502/2501 card is composed of a bunch of counters and trigger signals in the FPGA on board. There are seven timing signals related to the DAQ timing, which in turn influence the A/D, D/A process, and GPTC operation.
System Synchronization Interface SSI uses bi-directional I/O to provide flexible connections between boards. You can choose each of the seven timing signals and which board to be the SSI master. The SSI master can drive the timing signals of the slaves. You can thus achieve better synchronization between boards. Note that during power-up or reset, the DAQ board resets and uses its internal timing signals.
58 Operation Theory
5 Calibration This chapter introduces the calibration process to minimize AD measurement errors and DA output errors. 5.1 Loading Calibration Constants The DAQ-/DAQe-/PXI-2502/2501 card is factory-calibrated before shipment. The associated calibration constants of the TrimDACs firmware to the onboard EEPROM. TrimDACs are devices containing multiple DACs within a single package. TrimDACs do not have memory capability.
5.2 Auto-calibration Through the DAQ-/DAQe-/PXI-2502/2501 card auto-calibration feature, the calibration software measures and corrects almost all calibration errors without any external signal connections, reference voltage, or measurement devices. The DAQ-/DAQe-/PXI-2502/2501 card comes with an onboard calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured in the production line through a digital potentiometer and compensated in the software.
Appendix Waveform Generation Demonstration Combined with six counters, selectable trigger sources, external reference sources, and time base, the DAQ-/DAQe-/PXI-2502/ 2501 provides the capabilities to generate complex waveforms. Various modes shown below can be mixed together to generate waveforms that are even more complex. Although you can always load a new waveform to generate any desired waveform, we suggest using hardware capabilities to maximize the card’s efficiency and flexibility.
Iterative Generation w. Intermediate Space Utilize DLY2_counter to separate consecutive waveform generations in iterative generation mode. In this demo, the original standard sine wave is repeated several times as specified in IC_counter, with intermediate space determined by DLY2_counter. Piece-wise Generation When the value specified in UC_counter is smaller than the sample size of waveform, the waveform is generated piece-wisely. The intermediate space between each piece is determined by DLY2_counter.
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3. Our repair service is not covered by ADLINK's guarantee in the following situations: X Damage caused by not following instructions in the User's Manual. X Damage caused by carelessness on the user's part during product transportation. X Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers. X Damage caused by unsuitable storage environments (i.e. high temperatures, high humidity, or volatile chemicals).
