User`s guide

Operation Theorem • 17
4.4 A/D Data Conversion
A/D Data Transfer Modes
The A/D data are buffered in register, the software mush ready out the A/D
data after the DRDY bit goes “low” after software trigger the A/D.
A/D Conversion Sequence
In ACL-8113A, the A/D conversion can only be controlled by software based
on polling concept. That is, the A/D conversion trigger is issued by software,
and then checks the DRDY bit ( Data Ready Bit) of the A/D status register. If
the DRDY=1, the data conversion is still in progress. When the DRDY bit is
became to 0 ( Low), i.e. the A/D conversion is completed, and the converted
data can be read by your program.
The procedures of how to initiate and convert analog input to digit data is
listed step by step as following:
1. Define the base address of ACL-8113A card
e.g.
Base_addr = 0x220;
2. Set the desired input channel by MUX control register Base+ 10
e.g.
outportb( Base_addr + 10, 2);
3. Trigger the A/D conversion by writing any data to Base+12
e.g.
outportb( Base_addr + 12, 0);
4. Wait until the DRDY bit has became to low
e.g.
do status = inport( Base_addr + 5);
while( status & 0x10) == 0x10);
5. Get the converted data from Base+4 and Base+5
e.g.
lowByte = inportb( Base_addr + 4);
highByte = inportb( Base_addr + 5) & 0x0f;
6. Convert binary data to an integer value
e.g.
Data = lowByte + highByte * 256;
A/D Data Format
The range of A/D data read from the FIFO port is from 0 to 4095. As the A/D
gain is 1, the A/D signal range is roughly -10V ~ +10V or -5V~+5V (bi-polar)
and 0V~+10V (uni-polar). The relationship between the voltage and the value
is shown in the following table: