User`s guide

Registers Format • 11
3.2 A/D Data Registers
The ACL-8113A provides 32 single-ended A/D input channels, the converted
digital data will store in the A/D data registers after the conversion. The 12
bits A/D data is put into two 8 bits registers. The low byte data (8 LSBs) are
put in address BASE+4 and the high byte data (4 MSBs) are put in address
BASE+5. A DRDY bit is used to indicate the status of A/D conversion. DRDY
goes to “low” means A/D conversion is completed.
Address: BASE + 4 and BASE + 5
Attribute: read only
Data Format:
Bit 7 6 5 4 3 2 1 0
BASE+4 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
BASE+5 0 0 0 DRDY AD11 AD10 AD9 AD8
AD11 .. AD0: Analog to digital data. AD11 is the Most Significant Bit (MSB).
AD0 is the Least Significant Bit(LSB).
DRDY: Data Ready Signal.
1: A/D data is not ready
0: A/D conversion is completed.
It will be set to 1, when reading the low byte.
3.3 A/D Channel Control Register
This register is used to control the A/D channels to be converted. It's a write
only register. When the channel number is written to the register, the
multiplexer switches to the new channel and await for conversion.
Address: BASE + 10
Attribute: write only
Data Format:
Bit 7 6 5 4 3 2 1 0
BASE+10 X X X CL4 CL3 CL2 CL1 CL0
CLn: multiplexer channel number.
CL4 is MSB, and CL0 is LSB.
The combinations of CH4 ~ CH0 and their corresponding channel number is
listed in the table 3.2 below.