User`s manual

32 Operation Theory
The counter counts down on the rising edges of DLY1_counter
clock source after the start trigger signal. When the count
reaches zero, DAQ/PXI-2500 series starts to generate the
waveform. The DLY1_counter clock source can be software
selected from the Internal 40MHz Timebase, external clock
input (AFI-0), or GPTC output 0/1.
Post-Trigger or Delay-Trigger with Retrigger
Use post-trigger or delay-trigger with retrigger when users want
to gener-ate multiple waveforms with respect to multiple incom-
ing trigger signals. Users can set Trig_counter to specify the
number of acceptable trigger signals.
Figure 4-11 illustrates an example. Two waveforms are gener-
ated after the first trigger signal (Iterative Waveform Generation
is used in this example, please refer to Section 4.2 for details).
The board then waits for another trigger signal. When the next
trigger signal is asserted, the board generates two more wave-
forms. After three trigger signals, as specified in Trig_Counter,
no more triggers signals will be accepted unless software trig-
ger reset command is executed.
Note: Start Trigger signals asserted during waveform generation
process will be ignored.