NuDAQ-2500 Series High Performance Analog Output Multi-function Cards User’s Manual Manual Rev. 2.01 Revision Date: December 21, 2006 Part No: 50-12265-100 Advance Technologies; Automate the World.
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Table of Contents Table of Contents..................................................................... i List of Tables.......................................................................... iii List of Figures ........................................................................ iv 1 Introduction ........................................................................ 1 1.1 1.2 1.3 1.4 Features............................................................................... 1 Applications .........
4.2 4.3 4.4 4.5 4.6 Programmable Scan ..................................................... 19 D/A Conversion.................................................................. 26 Software Update ........................................................... 29 Waveform Generation ................................................... 29 General Purpose Digital I/O ............................................... 39 General Purpose Timer/Counter Operation ....................... 40 Timer/Counter functions basics .
List of Tables Table Table Table Table Table Table Table Table Table Table 3-1: 3-2: 4-1: 4-2: 4-3: 4-4: 4-5: 4-6: 4-7: 4-8: List of Tables Connector CN1 pin assignment .............................. 14 Connector CN2 pin assignment .............................. 14 Bipolar Input Range and Converted Digital Codes . 18 Unipolar Input Range and Converted Digital Codes 18 Trigger Modes and Corresponding Trigger Sources 20 Summary of Counters for Programmable Scan ...... 20 D/A Output Versus Digital Codes ...
List of Figures Figure 2-1: PCB Layout of DAQ-2502/2501............................... 11 Figure 2-2: PCB Layout of PXI-2502/2501................................. 11 Figure 4-1: Timing for Scan........................................................ 21 Figure 4-2: Post trigger .............................................................. 23 Figure 4-3: Delay trigger ............................................................ 23 Figure 4-4: Post trigger with retrigger.......................................
1 Introduction The DAQ/PXI-2500 SERIES is an advanced analog output card based on the 32-bit PCI/PXI architecture. High performance designs and state-of-the-art technology make this card ideal for waveform generation, industrial proc-ess control, and signal analysis applications in medical, process control, etc. 1.
X System Synchronization Interface (SSI) X A/D and D/A fully auto-calibration X Build-in programmable D/A external reference voltage compensator X Completely jumper-less and software configurable 1.
1.
Analog Input (AI) X Number of channels: 4 single-ended for DAQ/PXI-2502, 8 single-ended for DAQ/PXI-2501 X AD converter: LTC1416 X Max sampling rate: 400KS/s X Resolution: 14 bits X FIFO buffer size: 2K samples X Input range: Bipolar: ±10V, unipolar: 0~10V X Over voltage protection: Continuous ±35V maximum X Input impedance: 1GΩ | 6pF X Trigger mode: Pre-trigger, post-trigger, middle-trigger, and delay trigger X Data transfers: Programmed I/O, and bus-mastering DMA with scat-ter/gather X
General Purpose Timer/ Counter (GPTC) X Number of channel: 2 Up/Down Timer/Counters X Resolution: 16 bits X Compatibility: TTL/CMOS X Clock source: Internal or external X Max source frequency: 10MHz Analog Trigger (A.
Operating Environment X Ambient temperature: 0 to 55°C X Relative humidity: 10% to 90% non-condensing Storage Environment X Ambient temperature: -20 to 70°C X Relative humidity: 5% to 95% non-condensing 1.4 Software Support ADLINK provides versatile software drivers and packages for users’ different approach to building up a system. ADLINK not only provides pro-gramming libraries such as DLL for most Windows based systems, but also provide drivers for other software packages such as LabVIEW®.
D2K-LVIEW: LabVIEW® Driver D2K-LVIEW contains the VIs, which are used to interface with NI’s Lab-VIEW® software package. The D2K-LVIEW supports Windows 98/NT/2000/XP. The LabVIEW® driver is shipped free with the board. You can install and use them without a license. For detailed information about D2K-LVIEW, please refer to the user’s guide in the CD (\Manual\Software Package\D2K-LVIEW).
8 Introduction
2 Installation This chapter describes how to install DAQ/PXI-2500 SERIES cards. The contents of the package and unpacking information that you should be aware of are outlined first. DAQ/PXI-2500 SERIES performs an automatic configuration of the IRQ, and port address. Users can use software utility, PCI_SCAN.EXE to read the system configuration. 2.
Again, inspect the module for damages. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface. Note: DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED. You are now ready to install your DAQ/PXI-2500 SERIES.
2.
2.4 PCI Configuration 1. Plug and Play: As a plug and play component, the board requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the board information and system parameters. These system parameters are determined by the installed drivers and the hardware load seen by the system. 2. Configuration: The board configuration is done on a board-by-board basis for all PCI boards on your system.
3 Signal Connections This chapter describes the connectors of DAQ/PXI-2500 SERIES, and the signal connection between DAQ/PXI-2500 SERIES and external devices. 3.1 Connectors Pin Assignment DAQ/PXI-2500 SERIES is equipped with two 68-pin VHDCI-type con-nectors (AMP-787254-1). It is used for digital input / output, analog input / output, and timer/counter signals, etc. The pin assignments of the connectors are defined in the figures below.
PB3 24 58 PB2 PB1 25 59 PB0 PC7 26 60 PC6 PC5 27 61 PC4 DGND 28 62 DGND PC3 29 63 PC2 PC1 30 64 PC0 PA7 31 65 PA6 PA5 32 66 PA4 PA3 33 67 PA2 PA1 34 68 PA0 Table 3-1: Connector CN1 pin assignment Legend : Pin # Signal Name Reference Direction Description 1~4 AO_<0..3> AGND Output Voltage output of DA channel <0..3> 5 AOEXTREF_A/AI_0 AGND Input External reference for AO channel <0..
Pin # Signal Name Reference Direction 31,65,32,66, 33,67,34,68 PA<7,0> DGND PIO 35~46 AGND -------- -------- Analog ground Input External waveform trigger for AO channel <0..3> <4..
16 Signal Connections
4 Operation Theory The operation theories of the DAQ/PXI-2500 series are described in this chapter. The functions include A/D conversion, D/A conversion, Digital I/O, and General Purpose Counter / Timer. This operation theory will help you understand how to configure and program the DAQ/PXI-2500 series.
4.1 A/D Conversion When using an A/D converter, users should know the properties of the signal to be measured. In addition, users should setup the A/D configura-tions, including scan channels, input range, and polarities. The A/D acquisition is initiated by a trigger signal. The data acquisition will start once the trigger signal matches the trigger conditions. Converted data are queued into the FIFO buffer, and then transferred to the host PC's memory for further processing.
Magnitude Unipolar Input Range Digital code Midscale - LSB 4.999389V 2.499694V 1.249847V 1.249923V -FSR 0V 0V 0V 0V 3FFF 2000 Table 4-2: Unipolar Input Range and Converted Digital Codes Software Polling This is the easiest way to acquire a single A/D data. The A/D converter performs one conversion whenever the dedicated software command is executed. The software would poll the conversion status and read the A/D data back when it is available.
Please refer to Table 4-3 for a brief summary on Trigger Modes and their Trigger Sources. Trigger Sources Trigger Mode Description Post-Trigger Perform a scan right after the trigger occurs. Delay-Trigger Scan delayed by the amount of time programmed after the trigger Post/DelayTrigger with Retrigger Software Trigger Digital Trigger Analog Trigger Perform repeated scan while trigger occurs and it could be under Post-Trigger or De-lay- SSI AD Trigger Trigger mode.
The relationship between counters and acquisition timing is illustrated in Figure 4-1. Figure 4-1: Timing for Scan NOTE: 1. The maximum A/D sampling rate is 400KHz for DAQ/ PXI-2500 series therefore the minimum setting of SI2_counter is 100. 2. The Scan Interval can not be smaller than the interval of data Sampling Interval multiple by the Number of channels per Scan, i.e.
formed after the trigger signal is specified by the PSC_counter, as illustrated in Figure 4.1.2. The total acquired data length = (number_of_channels_enabled_for _scan_acquisition) * PSC_counter. Delay Trigger Acquisition Use delay trigger when users want to delay the scan after a trigger signal. The delay time is determined by the Delay_counter, as shown in Figure 4-3. The counter counts down on the rising edges of Delay_counter clock source after the trigger signal.
Figure 4-2: Post trigger Figure 4-3: Delay trigger Operation Theory 23
Figure 4-4: Post trigger with retrigger Bus-mastering DMA Data Transfer Bus Mastering DMA Mode In order to utilize the maximum PCI bandwidth, PCI bus-mastering DMA is used for high speed DAQ boards. The bus-mastering capability of the PLX PCI controller, takes over the PCI bus when it becomes the master. Bus mastering reduces the required size of on-board memory as well as CPU loading since data is directly transferred to the host PC’s memory without CPU intervention.
DMA with Scatter Gathering Capability In multi-user or multi-tasking OS such as Microsoft Windows, Linux, etc., it would be difficult to allocate a large continuous memory block due to memory fragmentation. PLX PCI controller provides scatter /gather or chaining mode to link non-continuous memory blocks into a linked list, so that users can transfer large amounts of data without being limited by the fragment of memory blocks.
4.2 D/A Conversion DAQ/PXI-2500 series offers flexible and versatile analog output scheme to fit users’ complex field applications. In order to take full advantages of DAQ/PXI-2500 series, we suggest users carefully read the following con-tents. Architecture There are up to 8-channel of 12-bit Digital-to-Analog Converter (DAC) available in the DAQ/PXI-2502. Four D/A channels are packed into one D/A group, i.e., DAQ/PXI-2502 contains two D/ A groups, and DAQ/PXI-2501 has only one D/A group.
latched. This ensures D/A conversions to be synchronized for each channel in the same D/A group. Users can utilize this property to perform multi-channel waveform generation without any phase-lag. Hardware controlled Waveform Generation FIFO is a hardware first-in first-out data queue, which holds temporary digital codes for D/A conversion. When DAQ/PXI2500 SERIES operates in Waveform Generation mode, the waveform patterns are stored in FIFO, with 8K maximum samples.
under heavy loading. Detailed function setup will be explained in Section 4.2.2. Note: When using waveform generation mode, all the four DACs in the same D/A group must be configured for the same mode. However, any one of the DAC can be disabled. If users need to use the software update mode, they can use another D/A group on the PXI/DAQ-2502. Setting up the DACs Before using the DACs, users should setup the reference source and its polarity. Each DAC has its own reference and polarity settings.
-FSR + LSB -Vref * (2046 / 2048) Vref * ( -FSR -Vref 1 / 4096) 0 0001 0000 Table 4-5: D/A Output Versus Digital Codes DAQ/PXI-2500 SERIES can generate standard and arbitrary functions, continuously or piece-wisely. Appendix A demonstrates possible wave-form patterns generated by DAQ/PXI2500 SERIES in combination with various counters, clock sources, and voltage references. Software Update This method is suitable for applications that need to generate D/A output controlled by user programs.
Signal Descriptions Valid Sources DAWR Write data to the DAC on the fal-ling edges of DAWR. Stop Stop Waveform Generation Internal Update External Update SSI Update Software Trigger Ext. Digital Trigger Analog Trigger Table 4-6: Trigger Signals and Corresponding Signal Sources Waveform Generation Timing Six counters interact with the waveform to generate different DAWR timing, thus forming different waveforms. They are described in Table 4-7.
imum setting of UI_counter is 40. Figure 4-8: Typical D/A timing of waveform generation (Assuming the data in the data buffer are 2V, 4V, -4V, 0V) Trigger Modes Post-Trigger Generation Use post-trigger generation when users want to generate waveform right after a trigger signal.
The counter counts down on the rising edges of DLY1_counter clock source after the start trigger signal. When the count reaches zero, DAQ/PXI-2500 series starts to generate the waveform. The DLY1_counter clock source can be software selected from the Internal 40MHz Timebase, external clock input (AFI-0), or GPTC output 0/1.
Figure 4-9: Post-Trigger Generation Figure 4-10: Delay-Trigger Generation Operation Theory 33
Figure 4-11: Post-Trigger with Retrigger Generation Iterative Waveform Generation Users can set IC_counter to generate iterative waveforms, no matter which Trigger Mode is used. The IC_counter stores the iteration number. Examples are shown in Figure 4-12 and 4-13. When IC_counter is disabled, the waveform generation will not stop until a stop trigger is asserted. For Stop Mode, please refer to Section 4.2 for details. An on-board data FIFO is used to buffer the waveform patterns for wave-form generation.
will be a 1/8-cycle sine wave for every waveform period. In other words, a complete sine wave will be generated for every 8-iterations. If value specified in UC_counter is larger than the sample size of waveform LUT, say, 32; the generated waveform will be a 2-cycle sine wave for every waveform period. In conjunction with different trigger modes and counter setups, users can manipulate a single waveform to generate different, more complex wave-forms. For more information, please refer to Appendix A.
Figure 4-13: Infinite iterative waveform generation w/Post-trigger (Assuming the digital codes in the FIFO are 2V, 4V, 2V, 0V) DLY2_Counter in iterative Waveform Generation To expand the flexibility of Iterative Waveform Generation, DLY2_counter was implemented to separate consecutive waveform generations. The DLY2_counter starts counting down right after a single waveform generation is completed. When it reaches zero, the next iteration of waveform generation will start as shown in Figure 4.2.3.
After a mode I stop trigger is asserted, the waveform generation stops immediately. Figure 4-14 illustrates an example. Stop Mode II After a mode II stop trigger is asserted, the waveform generation continues to generate a complete waveform then stops the operation. Take Figure 4-15 as an example. Since UC_counter is set to 4, the total generated data points must be a multiple of 4.
Figure 4-14: Stop mode I (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) Figure 4-15: Stop mode II 38 Operation Theory
Figure 4-16: Stop mode III 4.3 General Purpose Digital I/O DAQ/PXI-2500 SERIES provides 24-line general-purpose digital I/ O (GPIO) through a 82C55A chip. The 24-line GPIO are separated into three ports: Port A, Port B and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of each port can be indi-vidually programmed to be either inputs or outputs. Upon system startup or reset, all the GPIO pins are reset to high impedance inputs.
4.4 General Purpose Timer/Counter Operation Two independent 16-bit up/down timer/counter are embedded in FPGA firmware for users applications. They have the following features: X Direction of counting can be controlled via hardware or software. X Selectable counter clock source from either internal or external clock up to 10MHz. X Programmable gate selection. X Programmable input and output signal polarities, either active-high or active-low.
General Purpose Timer/Counter modes Eight programmable timer/counter modes are provided. All modes start operations following the software start command. The GPTC software reset command initializes the status of the counter and re-loads the initial value to the counter. Mode1: Simple Gated-Event Counting In this mode, the counter counts the number of pulses on the GPTC_CLK after the software start. Initial count value can be loaded via software. Current count value can be read-back by software at any time.
count value can be read-back by software. Figure 4-18 illustrates the operation where initial count = 0, up-counting mode. Figure 4-18: Mode 2 Operation Mode3: Single Pulse-width Measurement In this mode, the counter counts the pulse-width of the signal on GPTC_GATE in terms of GPTC_CLK. Initial count can be loaded via software. After the software start, the counter counts the number of active edges on GPTC_CLK when GPTC_GATE is active.
enable/disable counting. When GPTC_GATE is inactive, the counter halts the counting. Figure 4-20 il-lustrates the generation of a single pulse with pulse-delay of two and pulse-width of four. Figure 4-20: Mode 4 Operation Mode5: Single Triggered Pulse Generation This function generates a single pulse with programmable delay and pro-grammable pulse-width following an active GPTC_GATE edge. These software programmable parameters can be specified in terms of periods of the GPTC_CLK input.
After the software start, every active GPTC_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC_GATE trigger that occurs during the pulse generation would be ignored. Figure 4-22 illustrates the generation of two pulses with pulse delay of two and pulse-width of four.
value. Figure 4-24 illustrates the generation of two pulses with pulse delay of four and pulse-width of three. Figure 4-24: Mode 8 Operation 4.5 Trigger Sources We provide flexible trigger selections in DAQ/PXI-2500 SERIES. In addi-tion to software trigger, DAQ/PXI-2500 SERIES also supports external analog and digital triggers. Users can configure the trigger source for A/D and D/A processes individually via software. NOTE: A/D and D/A conversion share the same analog trigger.
Figure 4-25: Analog trigger block diagram Trigger Level digital setting Trigger voltage 0xFF 9.92V 0xFE 9.84V --- --- 0x81 0.08V 0x80 0 0x7F -0.08V --- --- 0x01 -9.92V 0x00 -10V Table 4-8: Analog trigger SRC1(EXTATRIG) ideal transfer characteristic The trigger signal asserts when an analog trigger condition is meet. There are five analog trigger conditions in DAQ/PXI-2500 SERIES.
Figure 4-26: Below-Low analog trigger condition Above-High analog trigger condition Figure 4-27 shows the above-high analog trigger condition, the trigger signal asserts when the input analog signal is higher than the High_Threshold voltage. The Low_Threshold setting is not used in this trigger condition.
Figure 4-28: Inside-Region analog trigger condition High-Hysteresis analog trigger condition Figure 4-29 shows the high-hysteresis analog trigger condition, the trigger signal asserts when the input analog signal level is higher than the High_Threshold voltage, where the hysteresis region is determined by the Low_Threshold voltage.
Figure 4-30: Low-Hysteresis analog trigger condition 4.6 Timing Signals In order to meet the requirements for user-specific timing or synchronizing multiple boards, DAQ/PXI-2500 SERIES provides a flexible interface for connecting timing signals with external circuitry or other boards. The DAQ timing of the DAQ/PXI-2500 SERIES is composed of a bunch of counters and trigger signals in the FPGA on board.
Figure 4-31: DAQ signals routing System Synchronization Interface SSI uses bi-directional I/O to provide flexible connections between boards. You can choose each of the 7 timing signals and which board to be the SSI master. The SSI master can drive the timing signals of the slaves. Users can thus achieve better synchronization between boards. Note that when power-up or reset, the DAQ board is reset to using its in-ternal timing signals.
5 Calibration This chapter introduces the calibration process to minimize AD meas-urement errors and DA output errors. DAQ/PXI-2500 SERIES is factory calibrated before shipment. The on-board high precision band-gap voltage reference together with TrimDAC compensates for unwanted offsets and gain errors, caused by environment variation or component aging. 5.
5.2 Saving Calibration Constants An on-board EEPROM is used to store calibration constants. In addition to a default bank that stores factory calibration constants, there are three user banks. Users can save the subsequently performed calibration constants in anyone of these user banks. ADLink provides software for users to save calibration constants in an easy manner. 5.
Appendix Waveform Generation Demonstration Combined with 6 counters, selectable trigger sources, external reference sources, and time base, DAQ/PXI-2500 SERIES provides the capabilities to generate complex waveforms. Various modes shown below can be mixed together to generate waveforms that are even more complex. Although users can always load a new waveform to generate any desired waveform, we suggest using hardware capabilities to maximize both efficiency and flexibility.
Iterative Generation w. Intermediate Space Utilize DLY2_counter to separate con-secutive waveform generations in itera-tive generation mode. In this demo, the original standard sine wave is repeated several times as specified in IC_counter, with intermedi-ate space determined by DLY2_counter. Piece-wise Generation When the value specified in UC_counter is smaller than the sample size of waveform, the waveform is generated piece-wisely. The intermediate space between each piece is determined by DLY2_counter.
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