User`s guide

Registers • 27
4.8 A/D & FIFO Status Register
Address: BASE + 28
Attribute: read
Data Format:
Bit 7 6 5 4 3 2 1 0
ACQ Full HFull Empty Trg_det SC_TC ADOR ADOS
Bit 15 14 13 12 11 10 9 8
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Bit 23 22 21 20 19 18 17 16
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Bit 31 30 29 28 27 26 25 24
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Table 11. A/D & FIFO Status Register
ACQ (Bit7): Read Only, set when acquisition is in progress.
Full (Bit6): Read Only A/D FIFO Full status (Fatal Error!)
0: FIFO Full
1: FIFO not Full
HFull(Bit5): Read only A/D FIFO Half Full status
0: FIFO Half Full
1: FIFO not Half Full
Empty (Bit4): Read Only A/D FIFO Empty status
0: FIFO Empty
1: FIFO not Empty
Trg_det (Bit3): Read/ Write 1 to clear External Digital Trigger Status
1: External Digital Trigger
0: No External Digital Trigger