User`s guide

Registers • 25
HL_sel(bit3): >31 channel selection (single ended)
1: when channel number is larger than 31
0: when channel number is smaller than or equal to 31
DIFF(bit1): Analog Input Signals Type
1: Differential
0: Single ended
UNIP(bit2): Analog Input Signals Polarity
1: Unipolar
0: Bipolar
U_CMMD (bit0): User Defined Common Mode Selection
1: User Defined Common Mode (Pin 1)
0: Local Ground of 9116 series
4.7 A/D & FIFO Control Register
Address: BASE + 28
Attribute: Write
Data Format:
Bit 7 6 5 4 3 2 1 0
SC_dis
Clear
Channel
Gain
Queue
Set
don
e
Clear
DFIF
O
Clear
Trg_de
t
Clear
SC_T
C
Clear
ADOR
Clear
ADOS
Bit 15 14 13 12 11 10 9 8
--- --- --- --- --- --- --- DMA
Bit 23 22 21 20 19 18 17 16
--- --- --- --- --- --- --- ---
Bit 31 30 29 28 27 26 25 24
--- --- --- --- --- --- --- ---
Table 10. A/D & FIFO Control Register