User`s guide

Appendix B • 57
Run-time
resources
Includes features such as
doorbell interrupts, I20 message
unit, and so on that must be
managed by the device driver.
Typically has only
configuration
registers; no device
driver is required.
Clocks Generates secondary bus clock
output. Asynchronous secondary
clock input is also supported.
Generates one or
more secondary bus
clock outputs.
Table 27: Features of the PCI-to-PCI Transparent Bridge
B.2 Operating Therory
The 21555 separates bus address into two independent memory spaces
and each space has its own BARs. Addition CSRs are added to help
control the address translations and interrupt events. The illustration
below shows this basic concept.
Figure 7: 21555 Bus Addressing
Any PCI transactions, which fall into the preset BAR window range, will be
transfer to the other side of the memory automatically. The same actions
will happen on both sides.
How do determine the actual memory range to be transacted? The 21555
implements three different classes of registers. The BARs record the
memory size and type (memory or I/O). The setup registers is used to
configure the transaction window size. Figure 7 shows how the setup
registers work.
Primary
Address Map
Secondary
Address Map
Translated
Base+Offset
Base+Offset