cPCI-6765(A) Intel 440BX with Mobile CPU 6U Compact PCI CPU CARD User’s Guide Recycled Paper
©Copyright 2003 ADLINK Technology Inc; All Rights Reserved. Manual Rev. 1.00: January 28, 2003 Part No. 50-15015-100 The information in this document is subject to change without prior notice in order to improve reliability, design and function and does not represent a commitment on the part of the manufacturer.
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Table of Contents List of Tables .......................................................................................................iv List of Figures.......................................................................................................v Outline of User’s Manual...................................................................................vi Chapter 1 Introduction....................................................................................... 1 1.1 Unpacking Checklist........
Chapter 2 Jumpers and Connectors............................................................17 2.1 cPCI-6765(A) Board Outline and Illustration.....................................18 2.2 Configuration ..........................................................................................19 2.2.1 SW1 (Reset)............................................................................19 2.2.2 S1, S2, S3 and S4 (Setting LAN1 and LAN2 for Front or Rear Access)...................................................
4.2 LAN Driver Installation ..........................................................................44 4.2.1 Software and Driver Support................................................44 4.2.2 Intel 82559 Driver Installation on Windows 98 ................45 4.2.3 INTEL 82559 Driver Installation on Windows 2000 ........46 4.2.4 Intel 82559 Driver Installation on Windows XP................47 4.2.5 Intel 82559 Driver Installation on Windows NT................48 Chapter 5 Utilities .........................
List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Power consumption with above configuration .........................14 Peripheral Connectivity Table......................................................16 Switch Cross-Reference Table..................................................
List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Bock Diagram of cPCI-6765(A) ......................................................... 4 Board Layout.......................................................................................18 Mounting Location of stand-off on 2.5” HDD ................................37 Watchdog Timer Architecture ..........................................................49 l_stat Signal Implementation .......
Outline of User’s Manual This manual is intended to assist users with understanding and configuring the cPCI-6765(A) 6U CompactPCI SBC and Rear I/O Transition Modules. It is divided into 5 chapters. Chapter 1, “Introduction”, gives an overview of the product features, applications, and specifications. Chapter 2, “Connectors and Jumpers”, this chapter outlines all the connectors and its pin defi nitions.
1 Introduction The cPCI-6765(A) CPU Board with Mobile Intel Pentium III Processor - M is a single board computer designed to work as a modular component in a high-performance CompactPCI system. It utilizes the Mobile Intel Pentium III Processor - M to provide extremely high PCI performance and the latest in memory and I/O technology combined with low power requirements.
1.1 Unpacking Checklist Check the shipping carton for any damages. If the shipping carton and contents are damaged, notify the dealer for a replacement. Retain the shipping carton and packing material for inspection by the dealer. Obtain authorization before returning any product to ADLINK. Check the following items are included in the package, if there is any missing items, contact your dealer: • The cPCI-6765(A) module (May be equipped with different speed or capacity of CPU, RAM, and HDD).
1.2 Features • PICMG 2.0 CompactPCI Specification R3.0 Compliant. • PICMG 2.1 CompactPCI Hot Swap Specification R2.0 Compliant. • PICMG 2.16 CompactPCI Packet Switch Backplane Specification node slot compatible. • PICMG 2.9 CompactPCI System Management Specification R1.0 Compliant. • Design for low power BGA2 Pentium-III CPU running at FSB 100MHz. • Supports operation in peripheral mode, non-J4 connector for inserting into H.110 Backplane.
1.3 Functional Block The following topics are an overview of the cPCI-6765(A) main features as shown in the functional block diagram below.
1.3.1 CompactPCI Bus Interface The cPCI-6765(A) operates in a 6U CompactPCI system. The CompactPCI standard is electrically identical to the PCI local bus standard but has been enhanced to work in harsh environments and support more peripheral slots. Additionally, when used in a Hot Swap compliant backplane and in accordance with the CompactPCI Hot Swap Specification, PICMG 2.1, Version 1.0, the cPCI-6765(A) supports hosting hot swappable peripherals in a powered system.
1.3.4 Supported Memory The cPCI-6765(A) supports two 144-pin SO-DIMM sockets and hence can accommodate u p to a maximum total memory size of 512MB. The memory type must be 3.3V SDRAM and can come in size of 32MB, 64MB, 128MB or 256MB. The entire memory array may be configured as either standard (un-buffered) SDRAM or buffered SDRAM and the DIMM sockets can be populated in any order. ADLINK factory provides pre-mounting memory for OEM project.
1.3.6 DMA Two enhanced DMA controllers are provided on the cPCI-6765(A) for use by the onboard peripherals. The cPCI-6765(A)'s DMA controllers reside in the Intel 82371EB (PIIX4E) device. 1.3.7 Real-Time Clock The real-time clock performs timekeeping functions and includes 256 bytes of general purpose, battery-backed, CMOS RAM. Timekeeping features include an alarm function, a maskable periodic interrupt, and a 100-year calendar. The system BIOS uses a portion of this RAM for BIOS setup information.
1.3.10 PCI Mezzanine Card (PMC) Interface The cPCI-6765(A) provides a location for one on-board PMC device with front panel access. The PMC interface is on the PCI Bus with PMC VIO default factory setting tied to 5.0V by 0-ohm resistors R33 and R34. If R33 and R34 are removed, and R38 and R49 are installed with 0 -ohm resistors, the PMC VIO is 3.3V. 1.3.
1.3.15 IEEE-1284 Parallel Port/Printer Interface The parallel I/O interface signals are routed to J5 providing signal connection for a DB25 on the cPI-R6765. This port supports the full IEEE-1284 specifications and provides the basic printer interface. Firmware will initialize the parallel port as LPT1 with ISA I/O base address of 378h. This default configuration also assigns the parallel port to IRQ7.
1.4 Specifications 1.4.1 cPCI-6765(A) Specifications General CompactPCI Features: • PCI Rev.2.1 compliant • PICMG 2.0 CompactPCI Rev. 3.0 compliant. • PICMG 2.1 CompactPCI Hot-swap specification Rev.2.0 compliant • PICMG 2.16 CompactPCI Packet Switch Backplane Specification node slot compatible. • PICMG . 2.9 CompactPCI System Management Specification R1.0 Compliant. Form Factor: • Standard 6U CompactPCI (board size: 233mm x 160mm) • 1-slot (4TE/HP, 20.32mm) wide, incl. space of 2.
CompactPCI interface: • cPCI-6765 is a peripheral board design, suitable in peripheral slots, operated as a peripheral card in distributed multi -processor architecture. • Intel 21555 non-transparent PCI-to-PCI bridge interface on J1. • 32-bit/33MHz PCI operation. • Supports both 5V and 3.
System Management Interface: • Qlogic Zircon CP Baseboard Management Controller (BMC) with 14 Kbytes SRAM internally. • Monitor onboard voltages, temperatures. • Support external 16-bit Flash ROM with a size of up to 1Mbyte (protected boot block required). IDE Ports: • Bus Master IDE controller supports two EIDE interfaces • One 44-pin secondary EIDE connector on front CPU module, supports on-board 2.
Watchdog Timer: • Programmable I/O port 3F0h and 3F1h to configure watchdog timer, programmable timer 1~255 seconds or 1~255 minutes • A LED indicator on front faceplate for watchdog timer status indication • Bundled easy-programming library for DOS, Windows 95, 98, NT Hardware Monitoring: • Winbond W83L784, monitoring CPU temperature, system temperature and DC Voltages PMC module support: • On-board one IEEEP1386.
Front Panel LEDs and switch: • Power status (green) • IDE activity indicator (red) • Ethernet port 1&2: 10/100Mb (amber), activity (Green) • Watchdog timer status or Auxiliary indicator (green) • Hot-swap status indicator (blue) • On-handle limit switch for soft power-off signal triggering • Flush tact switch for system reset Environment: • Operating temperature: 0 to 55°C • Storage temperature: -40 to 80°C • Humidity: 5% to 95% non-condensed • Shock: 15G peak-to-peak, 11ms duration, no
The cPCI-6765(A) is supplied with a heatsink allowing the processor to operate between 0º and approximately 55º C ambient with a minimum of 1 meter per second of external airflow. It is the users' responsibility to ensure that the cPCI-6765(A) is installed in a chassis capable of supplying adequate airflow. The maximum power dissipation of the processor at 850MHz (BGA2 package) is 29W. External airflow must be provided at all times.
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2 Jumpers and Connectors This chapter will familiarize the user with the cPCI-6765(A) before getting started, it will provide information about the board layout, connector definitions, jumper setup and setting the PMC VIO, This will includes the following information: • cPCI-6765(A) board outline and illustration • cPCI-6765(A) connectors pin assignments • cPCI-6765(A) jumpers setting and PMC VIO • cPCI-R6765 connector pin assignments Jumpers and Connectors • 17
2.
2.2 Configuration The cPCI-6765(A) has been designed for maximum flexibility and can be configured for specific applications. Most configuration options are selected through the BIOS Setup utility however some options cannot be software controlled and are configured with jumpers or by other means beside software The cPCI-6765(A) contains a push-button switch on the faceplate and several banks of jumper pin on the front and rear board.
2.2.2 S1, S2, S3 and S4 (Setting LAN1 and LAN2 for Front or Rear Access) For convenience with wiring, the cPCI-6765(A) allows for either front or rear LAN1 and LAN2 access. Note that although both LAN1 and LAN2 are available on the front and rear, the same LAN port (e.g. LAN1 front and LAN1 rear), cannot be access simultaneously, and are set by dipswitches S1, S2, S3 and S4. The table below lists the access configuration. LAN1 LAN2 S1 S2 Front All ON All OFF Rear or 2.
2.2.3 JP2, JP3, JP4 and JP5 (COM2 RS-232/422/485/485+ Selectable) on RTM As COM2 is RS-232/422/485 selectable, to operate in its different communication protocols, JP2, JP3, JP4 and JP5 must be set according to the table listed below. The numbers in the table indicate the pin number that needs to be shorted together.
2.2.5 Clear CMOS RTC status cPCI-6765(A) JP1 Clear CMOS 1-2 3 2 1 Normal operation 2-3 (Default) 3 2 1 Table 8: Clear CMOS RTC RAM The CMOS RAM data for real time clock (RTC) contains the date / time and password information. The button cell battery powers the CMOS when the system is power off. To erase the CMOS RAM data: 1. Unplug the cPCI-6765(A). 2. Short pins 1 and 2 of JP1. Then reinstall the jumper back to normal location. 3. Plug cPCI-6765(A) back to the chassis. Turn the power on.
2.3 cPCI-6765(A) Connector Pin Assignments 2.3.1 VGA Connector (Front and RTM) Signal Name Pin Pin Signal Name Red 1 2 Green Blue 3 4 N.C. GND 5 6 GND GND 7 8 GND N.C. 9 10 GND N.C. 11 12 N.C. HSYNC 13 14 VSYNC NC 15 Table 9: VGA Connector Pin Assignment 2.3.
2.3.3 PS/2 Mouse/Keyboard Connector (Front) Pin # Signal Function 1 KBDATA Keyboard data 2 MSDATA Mouse data 3 GND GND 4 +5V Power 5 KBCLK Keyboard clock 6 MSCLK Mouse clock Table 12: PS/2 Keyboard Pin Assignment 2.3.4 USB Connectors (Front and RTM) Signal Name Pin # Vcc 1 USB- 2 USB+ 3 Ground 4 Table 13: USB Connector Pin Assignment 2.3.
Pin header on RTM PIN SIGNAL FUNCTION P1 RDCDJ1 Data Carrier Detect P2 RDSRJ1 Data Set Ready P3 RRXD1 Receive Data P4 RRTSJ1 Request to Send P5 RTXD1 Transmit Data P6 RCTSJ1 Clear to Send P7 RDTRJ1 Data Terminal Ready P8 RRIJ1 Ring Indicate P9 GND Ground P10 NC No Connect Table 15: COM1 Pin Header on RTM 2.3.
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2.3.
2.3.
2.3.11 PMC Connectors PMC J11 Connector Signal Pin Pin TCK(3) 1 2 Signal -12V GND 3 4 INTA# INTC# INTB# 5 6 BUSMODE1#(1) 7 8 +5V INTD# 9 10 RESERVED (1) GND 11 12 +3.
PMC J12 Connector Signal +12V TMS (2) TDI (2) GND RESERVED (1) BUSEMODE2# (2) PCI RESET +3.3V PME AD[30] GND AD[24] IDSEL (AD[31]) +3.3V AD18 AD16 GND TRDY# GND PERR# +3.3V C/BEJ[1]# AD[14] GND AD[8] AD[7] +3.
2.3.12 CompactPCI Connectors CompactPCI J1: 32-bit PCI System/Peripheral PIN Z A B C D E F 25 GND +5V REQ64# ENUM# +3.3V +5V GND 24 GND S1AD[1] +5V V(I/O) S1AD[0] ACK64# GND 23 GND +3.3V S1AD[4] S1AD[3] +5V S1AD[2] GND 22 GND S1AD[7] GND +3.3V S1AD[6] AD[5] GND 21 GND +3.3V S1AD[9] S1AD[8] GND S1C/B3[0]# GND 20 GND S1AD[12] GND V(I/O) S1AD[11] S1AD[10] GND 19 GND +3.3V S1AD[15] S1AD[14] GND S1AD[13] GND 18 GND S1SERR# GND +3.
CompactPCI J2: 64-bit PCI System/Peripheral Pin Z A B C D E F 22 GND GA4 GA3 GA2 GA1 GA0 GND 21 GND Reserved 20 GND Reserved Reserved Reserved 19 GND 18 GND Reserved Reserved Reserved 17 GND Reserved 16 GND Reserved Reserved DEG# 15 GND Reserved FAL# 14 GND Reserved Reserved Reserved 13 GND Reserved 12 GND Reserved Reserved Reserved 11 GND Reserved 10 GND Reserved Reserved Reserved 9 GND Reserved 8 GND Reserved Reserved Reserved 7 GND Reserved 6 GND Reserved
COMPACTPCI J3: LAN, COM, KEYBOARD&MOUSE, FDD, USB, 1ST IDE PIN Z A B C D E F 19 GND GND GND GND GND GND GND 18 GND LPa_DA+ (TX+) LPa_DA (TX-) GND LPa_DC+ Lpa_DC- GND 17 GND LPa_DB+ (RX+) LPa_DB(RX-) GND LPa_DD+ Lpa_DD- GND 16 GND LPb_DA+ (TX+) LPb_DA (TX-) GND LPb_DC+ LPb_DC- GND 15 GND LPb_DB+ (RX+) LPb_DB(RX-) GND LPb_DD+ LPb_DD- GND 14 GND GND GND GND GND GND GND 13 GND PDACT# PDCS1# PDCS3# PDA0 PDA2 GND 12 GND PPDIAG PDCS16# PDIRQ14 PD
COMPACTPCI J5: COM, Printer, USB, 2 ND IDE PIN Z 22 GND B DTR2# C CTS2# D TXD2 E RTS2# F GND GND RXD2 DSR2# DCD2# GND GND AUTOFD# GND 19 GND 18 GND A RI2# RSV (CLK6) RSV (CLK5) GND PPD0 GND PPD1 SLCTIN# PPD2 17 GND SLCT GND PPD4 16 GND PBUSY PPD5 PE 15 GND PPD7 GND Reserved PINIT# GND RSV (REQ6#) GND RSV (REQ5#) GND SDA2 GND SDD0 GND SDD3 GND SDD9 GND LAN_RXD2 GND RSV (REQ4#) RSV (GNT2#) RSV (GNT1#) 21 GND 20 GND 14 13 12 11 10 9 8 7 6 5 4 GND PACK# SDCS3# GND SPDIAG GND GND
3 Getting Started This chapter gives a summary of what is required to setup an operational system using the cPCI-6765(A). Hardware installation and BIOS overview is discuss. 3.1 CPU Installation The cPCI-6765(A) CPU module supports a low power Mobile Intel Pentium-III, with a front side bus (FSB) of 100 MHz. This product is shipped with a CPU and a CPU heatsink pre-mounted on the board. Note: 3.
To install memory on to DM1 socket, please follow the following procedures carefully: 1. Ensure the cPCI system is power off. Remove the cPCI-6765(A) from chassis. 2. Hold the SO-DIMM and have its edge connector at a slight angle then insert into DM1 socket. Note that the SO-DIMM is keyed. 3. Push the SO-DIMM into the connector horizontally until it snaps into place and is firmly seated. 4. Check to make sure the SO-DIMM is inserted securely. 3.
3.3.1 HDD Installation for cPCI-6765(A) Find the HDD accessory pack inside your original package. (Users purchasing the OEM model, non-standard, customized or special configuration model, the HDD accessory package may not be included as part of the packaging. Please contact ADLINK dealers or sales representatives to purchase this accessory pack). 1. Check the master/slave setting of your 2.5” ATA HDD 2. Screw on 4 stand-offs to the HDD on the component side where there a 4 mounting holes available.
3.4 BIOS Configuration Overview This topic presents an introduction to the Award PnP BIOS Setup Utility. For more detailed information about the BIOS and other utilities, see the BIOS Manual. The BIOS has many separately configurable features. These features are selected by running the built-in Setup utility. System configuration settings are saved in a portion of the battery-backed RAM in the real-time clock device and are used by the BIOS to initialize the system at boot up or reset.
3.5 Operating System Installation For more detailed information about your operating system, refer to the documentation provided by the operating system vendor. Install peripheral devices. CompactPCI devices are automatically configured by the BIOS during the boot sequence. Most operating systems require initial installation on a hard drive from a floppy or CDROM drive. These devices should be configured, installed, and tested with the supplied drivers before attempting to load the new operating system.
4 Driver Installation To install the drivers for the cPCI-6765(A), refer to the installation information in this chapter. Basic information is presented in this section, however, for more detailed installation information for non-Windows Operating Systems, refer to the extensive explanation inside the ADLINK CD.
4.1 VGA Drivers Installation This section provides information on how to install the VGA driver that come in the CD with the package. Please follow the instructions carefully in this section. Note that there must be relevant software installed in your system before you are permitted to install the VGA driver. 4.1.1 Display Driver for Windows 98/ME The following section describes the normal procedures for installing the display driver for Windows 98/ME. Installing the Drivers for Windows 98/ME 1.
7. You will then see a warning panel about Third Party Drivers, Click yes to finish the installation. 8. Once the installation is completed, the system must be shut down and restarted for the new drivers to take effect. Note: After installing the VGA/AGP drivers, and you discover the driver does not work probably. This may be caused by not installing Windows NT service pack beforehand. Ensure to install Windows NT service pack 6 or higher version to enable AGP capability. 4.1.
4.1.4 Installing Drivers for Windows XP The following section describes the normal procedures for installing the display driver for Windows XP. Installing the Drivers for Windows XP 1. Click the "Start" button, then select the "Settings" tab and click on “Control Panel". 2. Click on the “Performance and Maintenance” icon and select the “system” icon 3. Click on the “Hardware” tab, and then click on the “Device Manager” tab 4.
4.2 LAN Driver Installation This section describes the LAN driver installation procedures for the onboard Ethernet controller Intel 82559. The Intel 82559 is a 32-bit 10/100MBps Ethernet controller for the PCI local bus-compliant PC. It supports the bus mastering architecture, and Auto-negotiation features which makes it possible to combine a common Ethernet cable (RJ-45 connector with twisted-pair cabling) for use with both 10Mbps and 100Mbps connection.
4.2.2 Intel 82559 Driver Installation on Windows 98 Windows 98 will attempt to install a standard LAN driver automatically. To guarantee compatibility, manually install the most updated LAN driver, which is stored in the ADLINK CD. After installing Windows 98, update to the most updated driver using the following procedures. 1. Boot Windows 98, Click Start. Select Settings then double-click the Control Panel. 2. Double-click on the System icon, click on the Device Manager tab. 3.
4.2.3 INTEL 82559 Driver Installation on Windows 2000 Windows 2000 will attempt to install a standard LAN driver automatically. To guarantee compatibility, manually install the most updated LAN driver, which is stored in the ADLINK CD. After installing Windows 2000, update to the most updated driver using the following procedures 1. Boot Windows 2000, Click Start. Select Settings then double-click on the Control Panel. 2. Double-click System icon, click Hardware tab, then click Device Manager button. 3.
4.2.4 Intel 82559 Driver Installation on Windows XP Windows XP will attempt to install a standard LAN driver automatically. To guarantee compatibility, manually install the most updated LAN driver, which is stored in the ADLINK CD. After installing Windows XP, update to the most updated driver using the following procedures. 1. Boot into Windows XP, Click Start. Select Settings then double-click the Control Panel. 2. Double-click System icon, click Hardware tab, then click the Device Manager button. 3.
4.2.5 Intel 82559 Driver Installation on Windows NT Before installing the LAN driver on Windows NT, copy the LAN driver files in the CD to a floppy diskette. Insert a new diskette into drive A: then type the following batch command under a DOS environment to copy the relative NT LAN drivers X:\CHIPDRV\LAN\100PDISK. Windows NT may ask to install a LAN driver from its own library of drivers. To guarantee compatibility, manually updated the LAN driver, which comes with the ADLINK CD.
5 Utilities This chapter explains the operation of the cPCI-6765(A)’s watchdog timer. It provides an overview of the watchdog operation and features; as well sample codes are stored in the CD to help you learn how the watchdog timer works. 5.1 Watchdog Timer Overview The primary function of the watchdog timer is to monitor the cPCI-6765(A)’s operation and to reset the system if the software fails to function as programmed.
The cPCI-6765(A)’s custom watchdog timer circuit is implemented in a programmable logic device. The watchdog timer contains a "Control and Status Register". The register allows the BIOS or user applications to determine if a watchdog time out was the source of a particular reset. • The watchdog times out after a selected timeout interval. • A hard reset occurs. The timeout period is 1 – 255 seconds or 1 – 255 minutes. 5.1.
5.2 Hardware Doctor Utility This section introduces the Hardware Doctor Utility that comes with the CPU board in conjunction with the onboard hardware monitoring function. The section briefly describes the function of the utility. Hardware Doctor is a self-diagnostic system for PC’s and must be used with the Winbond W83L784 IC series products. It helps to protect the PC Hardware by monitoring several critical items including Power Supply Voltage and CPU & System temperature.
A Appendix A A.1 CPCI-6765A System Mode Hot Swap Insert behavior • Ejector open – supplies 3.3V and 5V early voltages, hot-swap LED turn on to indicate on-board powers off. • Ejector close–the LTC1643 hot swap controller turn on all supply voltage and hot-swap LED turns off. Removed behavior • Ejector open– generates a power down button signal, software shuts down system and turns on hot-swap LED to indicate it is safe to removed the board from the live slot. A.
A.2.1 Hot Swap Controller Hardware Interface The US1010 low dropout regulator generates the 1V pre-charge voltage for the data bus lines. The output of the US1010 is set to 1.8V, but the voltage is further dropped by the 1N4148 diode to generate the 1V. The pre-charge circuit is capable of sourcing and sinking 40mA. The hot-swap controller also supports bi-directional pin, l_stat. This signal is a micro-switch sensor input and a LED control output.
A.2.2 Insertion and Removal Process The flow chart below is the 21555 Hot-Swap controller insertion and removal process.
The flow begins from card insertion. This occurs when reset: either p_rst_l or s_rst_in_l, is asserted and l_stat is sampled high. In the Local Reset state, all outputs are tristated, except the secondary reset output, s_rst_l. The state of the micro-switch controls the state of the LED in the Local Reset state. As long as the micro-switch is closed in this state, the LED is on; the 21555 do not drive l_stat in this state.
B Appendix B B.1 21555 Application Notes The cPCI-6765 incorporates an INTEL 21555 Non-transparent PCI-to-PCI Bridge to operate at peripheral mode. As a peripheral card, it is recognized as a device on the host bus as well as the local side. So an extra device driver is needed to make it work. This is the most i mportant feature. In order to map two separated memory spaces so it implements two sets of type 0 PCI BARs plus some CSRs.
Run-time resources Clocks Includes features such as doorbell interrupts, I20 message unit, and so on that must be managed by the device driver. Generates secondary bus clock output. Asynchronous secondary clock input is also supported. Typically has only configuration registers; no device driver is required. Generates one or more secondary bus clock outputs. Table 27: Features of the PCI-to-PCI Transparent Bridge B.
Figure 8: Setup Register The translation base registers hold the addresses to be trans lated to. As mentioned above, if an address translation is triggered, the 21555 will look up the base register and calculate the target-translated address. Figure 8 illustrates the actions. Figure 9: Translation of Base Registers The 21555 also provide different methods to decode the target address. Refer to the 21555’s user manual for advance usage.
B.3 Programming notes In this section, we will discuss the detailed programming techniques. Including sample codes. If needed, modify the source to fit the actual environment. Source codes are packed within the All-In-One CD-ROM.
B.3.1 Sample Code Test platform: Linux kernel 2.4.18 for x86 CPU B.3.2 Search and Register device … dev=pci_find_subsys(VENDOR,DEVICE,SUBSYSTEM_VENDOR,SUBSYSTEM_ DEVICE,NULL); …. B.3.
PDEBUG("R2D2DeviceMapMem: calling hal translate\n"); SYSaddr = ioremap(PCIaddr,memSize); if (SYSaddr) { pDE->BAR2VirtualWindowAddress = SYSaddr; pDE->cachedDisk = false; PDEBUG("R2D2DeviceMapMem: Remote DiskBuffer mapped in uncacheable memory @ %p\n",SYSaddr); } else { PWARN("R2D2DeviceMapMem: unable to map Remote DiskBuffer \n"); return 1; //map failed } //map BAR3 pDE->BAR3VirtualWindowAddress = 0; memSize = pDE->thisPhysicalMemorySize[BAR3]; PCIaddr = pDE->thisPhysicalMemoryAddr[BAR3]&0xFFFFFFF0; PDEBUG(
B.3.4 Create Memory Buffer for Other Side int allocatePools(Spull_Dev *pDE) { ULONG address; int order = bytes_to_order(SPULL_SIZE*1024); int bytes; do { address = __get_free_pages(GFP_KERNEL, order); if (address != 0) /* Success */ { bytes = PAGE_SIZE << order; memset((void *) address, 0, bytes); pDE->RemoteUserBufferSize=bytes; PDEBUG("allocatePools: Allocating Common Buffer for %0lX bytes.
} B.3.5 Syncing with Setting and Exchange Base address if (pDE->ThisInterface == PRIMARY_INTERFACE) { writel(pDE->RemoteUserBufferLogicalAddr, DB_ADDR(pDE->BAR0VirtualWindowAddress,BAR_UP_BAR2_XLAT_BASE)); value = sync_wait; done = false; PDEBUG("R2D2FindInitDevice: Waiting for signal from Secondary Interface.
DB_ADDR(pDE->BAR0VirtualWindowAddress,BAR_DOWN_BAR2_XLAT_BASE)); value = sync_wait; done = false; PDEBUG("R2D2FindInitDevice: Waiting for signal from Primary Interface.
B.3.5 Init Interrupt Register int initializeInterrupt(Spull_Dev *pDE) { int result; PDEBUG("initInterrupt: Entered Interrupt Initialization routine.
B.3.6 Driver Installation Procedures Intel 21555 Sample Driver User Manual Introduction: This is a sample driver that enables the non-transparency PCI-to PCI bridge mode access and maps the memory to the other side of the bridge. We have configured its’ application as a ram disk, so no extra utilities are required. Installation: The driver path: X:\NuIPC\6765\Intel 21555 1. Copy file: copy R2d2.SYS c:\winnt\system32\drivers 2. Update the registry: regini r2d2.ini 3.
C Appendix C C.1 Baseboard Management The Zircon CP BMC is used to manage all aspects of system boards. The hardware features are summarized as follows.
• Support SDR and sensor reading C.1.1 Flash Organization C.1.2 Host Interface The Host and system BIOS communicate with Zircon through the LPC-bus. Two software interface types are provided: • Keyboard Controller Style Interface (KCS) – The KCS interface model consists of a set of two registers. One of the registers is the Data In/Out register. The other is the Command/Status register – Com mand data is written to and Status information is read from the register address.
• Block Transfer (BT) – Zircon CP’s BT interface provides 128-byte (each) Host-to-BMC and BMC-to-Host FIFOs. The interface provides the three-register set specified in the IPMI specification – BT_CTRL, HOST2BMC/BMC2HOST, and BT_INTMASK. As in the KCS interfaces, each register’s system address is programmable. The FIFOs remain IPMI v1.1 compliant while providing an operational extension to the specification for queued operation.
C.1.4.1 Global Commands • GET DEVICE ID – Used to retrieve the intelligent device’s gerneral information. • COLD RESET – The firmware issues a reset pulse to reset itself and to generate a reset for FLASH memory. • WARM RESET - Zircon responds to this command by executing a cold reset. This is done to ensure coherence across the system interface. • GET SELF-TEST RESULTS – Directs the device to return the results of its Self-Test.
• MASTER WRITE-READ I2C – Zircon provides access to non-intelligent devices on the private I2C bus and IPMB behind the management controller via the MASTER WRITEREAD I2C command. C.1.4.3 Event Commands The ‘Sensor/Event’ Network Function is used for device functionality related to transmission, reception and handling of ‘Event Messages’ and platform events. Zircon supports the following event commands: • SET EVENT RECEIVER – Tells a controller where to send Event Messages.
• RESERVE SDR REPOSITORY – Sets the present “owner” of the repository, as identified by the “Software ID” or by the requesters Slave Address from the command. • GET SDR – Returns the sensor record specified by Record ID. • GET SDR REPOSITORY TIME – Returns the time for the SDR Repository device. • SET SDR REPOSITORY TIME– Sets the time for the SDR Repository device. • ENTER SDR REPOSITORY UPDATE MODE – Used to enter SDR Repository Update Mode.
• CLEAR SEL – Clears all records from the SEL and provides status of the operation. • GET SEL TIME – Returns the time from the SEL device. • SET SEL TIME - Initializes the time in the SEL device. C.1.4.7 Chassis Commands • GET POH COUNTER – The firmware returns system up time since last power cycle. C.1.4.8 BMC Watchdog Timer Commands The following commands are supported for the firmware. • RESET WATCHDOG TIMER – Used to start and restart the watchdog timer.
C.1.5 Sensor Data Record The cPCI-6765 has pre-defines SDRs such as voltages, system temp. Sensor Sensor Normal Device Remark Number name Reading 0x20 Vcore 1 Zircon 1.15 0x21 5V Zircon 5 0x22 3.3V Zircon 3.3 0x23 Vcore 2 Zircon 1.15 0x24 12V Zircon 12 0x11 Int temp ADM1026 30 Temp inside ADM1026 0x12 Vbat ADM1026 3 0x13 CPU1 temp ADM1026 30 0x14 CPU2 temp ADM1026 30 0x15 3.3V Main ADM1026 3.3 0x16 5V ADM1026 5 0x17 Vcore 1 ADM1026 1.15 0x18 12V ADM1026 12 0x19 -12V ADM1026 -12 0x1A Vtt ADM1026 1.25 0x1B 2.
outside or remote. We can us e this command to archieve this goal. C.1.6.1 Dynamic IPMB address allocation ü Query current GA and I2C address Action Byte Code Description 0 0xC0 NetFn/LUN for OEM, 0 Request 1 0xF0 OEM defined command 0 Complete Code 00 means OK 1 IPMB address 0xB0-0xEC besides C2 is reserved Response 2 GA reading 0x1-0x31 is valid 4 Internal value Don’t care ü Rescan GA In hot swap insertion time, BMC receive power from long pin but GA pins still isolated and cause the reading incorrect.
ü Get Event Autoforward Status Action Byte Code Description 0 0xC0 NetFn/LUN for OEM , 0 Request 1 0x11 OEM defined command Respons 0 Complete Code 00 means OK e 1 Current value Current control value C.1.6.3 Host System Reset This command will pull low the reset button for one second then put it back to high.
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4. Customers are responsible for the fees regarding transportation of damaged products to our company or to the sales office. 5. To ensure the speed and quality of product repair, please download an RMA application form from our company website www.adlinktech.com. Damaged products with RMA forms attached receive priority. For further questions, please contact our FAE staff. ADLINK: service@adlinktech.com Test & Measurement Product Segment: NuDAQ@adlinktech.
