User`s manual

18 Chassis Overview
2.3.6 Trigger Bus
The trigger bus is a 8-lines bus that connects all PXI slots in the
same PCI segment. The trigger bus can be used to provide inter-
module synchronization mechanism. PXI modules can transmit
trigger or clock signals to one another through trigger bus, allow-
ing precisely timed responses to asynchronous external events
the system is monitoring or controlling.
2.3.7 System Reference Clock
PXIS-2719 supplies the PXI 10MHz system reference clock
(PXI_CLK10) to each peripheral slot for inter-module synchroniza-
tion. An independent buffer (having source impedance matched to
the backplane and a skew of less than 1 ns between slots) drives
the clock signal generated from a high-precision oscillator to each
peripheral slot.
This common reference clock signal can be used to synchronize
multiple modules in a PXI chassis.