Specifications

2Introduction
on the 66MHz PCI bus to achieve the full communication band-
width between the LAN and CPU. These two ports are connected
to J3 (or rear I/O) which conform to the PICMG 2.16 specification.
The third LAN port uses a 82541PI GbE controller on the 32-
bit/33MHz PCI bus.
A Management Controller (BMC) (which follows the Intelligent
Platform Management Interface (IPMI) v1.0 specification), is built
into the system to meet the demands of high reliability and ser-
viceability.
Please refer to the following block diagram for the cPCI-6840
architecture.
Figure 1-1: cPCI-6840 Block Diagram
CPU
PENTIUM M
SOUTH BRIDGE
HANCE RAPIDS
6300ESB
NORTH
BRIDGE
855GME
DDR SODIMM x2
TOTAL MAX 2GB
J3
RGB DB-15
OUTPUT
GIGA LAN
82546
DUAL PORT
Upper
PMC
Lower
PMC
UNIVERSAL
BRIDGE
PLX PCI6540
J5
J3
PIM
or
RIO
PICMG 2.16
OR
REAR IO
GIGA LAN
82541
SINGLE PORT
BMC
FWH
CPCI
BACKPLANE
J3USB2.0 2/3
USB2.0 0/1
SIDE J5
PIDE
SATA J5
SERIAL
PORT 1
SERIAL
PORT 0
J5
PSB
100MHz
4x
DDR 100MHz 2x
SINGLE CHANNEL
HI1.5
66MHz
4x
PCI
33MHz/32bits
PCI
66MHz/64bits
PCI
66/64
GIGA
LAN
PMC
REAR IO
LPC
33MHz/4bits
SERIAL
PORT
SERIAL
ATA
UATA
100
USB
2.0
RGB
RGB DB-15
OUTPUT
J3
LVDS A
LVDS A
CHRONTEL
CH7301A-T
DVO TO DVI
J3
TMDS
CONNECTOR
DVO C
SIO
W83627HG
J3
KBMS
KBMS
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