User`s guide

46  Operation Theorem
Pacer Trigger Source
The counter 1 and counter 2 are cascaded together to generate the timer
pacer trigger of A/D conversion. The frequency of the pacer trigger is
software controllable. The maximum pacer signal rate is 2MHz/4=500K
which excess the maximum A/D conversion rate of the ACL-8316/12. The
minimum signal rate is 2MHz/65535/65535, which is a very slow frequency
that user may never use it.
General Purpose Timer/ Counter
The counter 0 is free for users' applications. The clock source, gate control
signal and the output signal are sent to the connector CN3. This general
purpose timer/counter can be used as event counter, frequency generator or
used for measuring frequency and others functions.
I/O Address
The 8254 in the ACL-8316/12 occupies 4 I/O address as shown below.
BASE + 0 LSB OR MSB OF COUNTER 0
BASE + 1 LSB OR MSB OF COUNTER 1
BASE + 2 LSB OR MSB OF COUNTER 2
BASE + 3 CONTROL BYTE
The programming of 8254 is controlled by the registers BASE+0 to BASE+3.
For more detailed information, please refer to Intel's data sheet (see
“http://support.intel.com/support/controllers/peripheral/231164.htm”).
Control Byte
Before loading or reading any of these individual counters, the control byte
(BASE+3) must be loaded first. The format of the control byte is:
Bit 7 6 5 4 3 2 1 0
SC1 SC0 RL1 RL0 M2 M1 M0 BCD
z SC1 & SC0 - Select Counter ( Bit7 & Bit 6)
SC1 SC0 COUNTER
0 0 Select Counter 0
0 1 Select Counter 1
1 0 Select Counter 2
1 1 ILLEGAL