User`s guide

38  Operation Theorem
FIFO Half-Full Interrupt Transfer
By properly programming the interrupt control register, the ACL-8316
provides FIFO half-full interrupt. As the FIFO is enable and be half-full, an
interrupt is inserted and the corresponding ISR will be invoked. The ISR can
read at least 512 sampling data because of the FIFO size is 1K sample. This
mode can tolerate more time delay and it is interrupt driven, therefore, it is
very suitable for Windows applications. The maximum 100 kHz sampling rate
can be also applied under this mode for high speed applications.
DMA Transfer
As the DMAENA bit of the A/D mode control register is set, the DMA (Direct
Memory Access) mode is enable and the interrupt resource will be occupied
by the terminal counting (TC) signal of the DMA controller. The DMA allows
data to be transferred directly from A/D data register to the PC memory at the
fastest possible rate without using any CPU time. The A/D data is
automatically transferred to PC's memory after conversion is complete.
The DMA transfer mode is very complex to program. It is recommended to
use the high level program library to operate this card. If you wish to program
the software which can handle the DMA data transfer, please refer to more
information about 8237 DMA controller.