User`s guide

28  Registers Format
3.12 DA Mode Control Register
Address : BASE + 13
Attribute : write
Data Format:
Bit 7 6 5 4 3 2 1 0
X X X X X X DA_FMT DA_MD1
Address : BASE + 13
Attribute : read
Data Format:
Bit 7 6 5 4 3 2 1 0
X X X X FF_ENA STYP DA_FMT DA_MD1
The D/A operation and D/A data format are controlled by this register and
the jumper JP8. The lower two bits are programmable and can be read
back too. Another two bits, the FIFO enable (FF_ENA) bit and the A/D
signal type (STYP) bit, are read only.
These two DA channels are set as transparency mode or double buffer
mode by DA_MD1 bit and jumper JP8 setting. The versatile operation
functions are shown as following table. The default setting of the JP8 is
TP and initial state of DA_MD1 is 0 too. Therefore, the DA channels are
default set as transparency mode. However, if user want to default set
double buffered mode when system power on, he can set JP8 to ‘DB’
externally. Even if the power on state is double buffer mode, the users still
can set DA_MD1 to 1 to change the DA channels to transparency mode.
JP8 Status
(hardware)
DA_MD1
(software)
DAs Control Mode
0 0 Transparency mode
0 1 Double buffer mode
1 0 Double buffer mode
1 1 Transparency mode
DA_FMT:
0: DA data value is in two‘s complement mode which the same as AD.
1: DA data value is in binary mode.
FF_ENA:
0: means FIFO is reset
1: means FIFO is enable.
STYP:
0: A/D signal sources are differential input.
1: A/D signal sources are signal ended.