User`s guide

24  Registers Format

3.6 Interrupt Source Control Register

The interrupt source of ACL-8316 is controlled by both of this register and

the A/D mode control register. The DMAEAN bit in A/D mode control

read back on the same port.

Address : BASE + 11

Attribute : read and write

Data Format:

Bit 7 6 5 4 3 2 1 0

X X X X X X IS1 IS0

When DMAENA is set (DMA enable), interrupt must come from TC

(terminal count) signal to indicate DMA transfer ending. However, when

the DMAENA is cleared (DMA disable), the interrupt source is set as

following table.

IS1 IS0 Interrupt Sources

0 0 A/D EOC

0 1 External interrupt source (1)

1 0 Internal Pacer Interrupt

1 1 FIFO half full (2)

Note(1) The external AD trigger signal can be used as external interrupt

source under this mode.

Note(2) The FIFO half full interrupt and DMA can not be run concurrently.

But the FIFO can still be read even the DMA is enable.