User`s guide

Registers Format  21
Note
: The ACL-8316/12 includes both 8 bits & 16 bits I/O ports. The AD
Data, DA channels, and digital I/O ports are 16 bits port. All the
others are 8 bits I/O port.
The 16-bit I/O data ( A/D, D/A and DIO) have to access via 16-bit
I/O operation.
3.2 A/D Data Registers
The value of AD data register is directly read from AD converter which
address is base address + 4. The A/D data is updated whenever AD is
triggered. The AD FIFO data is read from FIFO chips which address is
base address + 6, however, the AD data read from FIFO may be not in
‘real time’. The FIFO data should be read with FIFO control. The AD
FIFO port is enable only after the FF_ENA bit in A/D mode control register
is set.( refer to section 4.3)
Address : BASE + 4 and BASE + 6
Attribute : read only
Data Format:
(1) ACL-8312 (using 12 bits ADC)
Bit 15 14 13 12 11 10 9 8
AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4
Bit 7 6 5 4 3 2 1 0
AD3 AD2 AD1 AD0 0 0 0 0
AD11 .. AD0: Analog to digital data. AD11 is Most Significant Bit of the 12
bits digits and AD0 is Least Significant Bit.
(2) ACL-8316 (using 16 bits ADC)
Bit 15 14 13 12 11 10 9 8
AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8
Bit 7 6 5 4 3 2 1 0
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
AD15 .. AD0: Analog to digital data. AD15 is Most Significant Bit of the 16
bits digits, and AD0 is Least Significant Bit.
Note:
The 12 bits of A/D data of ACL-8312 are located on the 12 MSBs
and the 4 LSB is zero alwayse. Users can consider the ACL-8312,
which is of only 12 bit resolution, is the special case of the ACL-
8316.