NuDAQ® ACL-8316/8312 16/12-bit High Performance DAS Cards with 1K FIFO User’s Guide Recycled Paper
©Copyright 1996~2000 ADLINK Technology Inc. All Rights Reserved. Manual Rev. 2.50: November 9, 2000 Product no: 50-11016-100 The information in this document is subject to change without prior notice in order to improve reliability, design and function and does not represent a commitment on the part of the manufacturer.
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Table of Contents Chapter 1 Introduction ..................................................... 1 1.1 1.2 1.3 1.4 Features .................................................................................3 Applications............................................................................3 Specifications.........................................................................4 Software Support ...................................................................6 1.4.1 1.4.2 Programming Library.........
3.9 3.10 3.11 3.12 3.13 3.14 Clear Interrupt Register........................................................27 Software A/D Trigger Register.............................................27 DA Data Registers ...............................................................27 DA Mode Control Register ...................................................28 Digital I/O register ................................................................29 Internal Timer/Counter Register .......................................
5.21 5.22 5.23 5.24 5.25 5.26 5.27 5.28 5.29 5.30 5.31 _8316_AD_Aquire................................................................59 _8316_AD_DMA_Start ........................................................60 _8316_AD_DMA_Status......................................................61 _8316_AD_DMA_Stop.........................................................62 _8316_AD_INT_Start...........................................................62 _8316_AD_INT_Status ...........................................
How to Use This Guide This manual is designed to help you use the ACL-8316/12. The manual describes how to modify various settings on the ACL-8316/12 card to meet your requirements. It is divided into six chapters: Chapter 1: "Introduction", gives an overview of the product features, applications, and specifications. Chapter 2: "Installation", describes how to install the ACL-8316/12.
1 Introduction The ACL-8316/12 series DAS cards are high resolution and high performance data acquisition card based on the 16-bit PC/ISA Bus architecture. Both ACL-8316 and ACL-8312 share a common architecture and core features making each card is ideal for data logging and signal analysis applications. The ACL-8316/12 series features continuous, high speed, gap-free data acquisition under Windows or DOS environments.
2 • Introduction REF 0 IN < < . . . [Analog Input] CH 15 CH 1 CH 2 CH 0 REF 1 IN GND D/A 1 OUT GND D/A 0 OUT MUX SCAN CONTROL B U S I N T E R N A L DATA BUFFER DMA SELECT 5, 6, 7 DACK DRQ EXT.CLK Figure 1.1 ACL -8316/12 BLOCK DIAGRAM INTERRUPT IRQ SELECT TRIG LOGIC 16 BIT DIGITAL INPUT REGISTER EXTERNAL TRIG SOFTWARE TRIG PACER TRIG DO 15 . . . DO 1 DO 0 DI 15 . . .
1.
1.3 Specifications Analog Input (A/D) z Converter: ADS7805 or equivalent for ACL-8316 ADS7804 or equivalent for ACL-8312 z Resolution: 16-bit ( ACL-8316), 12-bit ( ACL-8312) z ADconverter type: successive approximation type z Number of channels: 16 single-ended or 8 differential z Conversion Time: 8 µ sec z Maximum sampling rate: 100KHz multiplexing z Input Range: (programmable) Bipolar: ± 10V, ± 5V, ±2.5V, ±1.
Digital I/O ( DIO) z Channel: 16 TTL compatible inputs and outputs z Input Voltage: Low: Min. 0V ; Max. 0.8V High: Min. +2.0V z Input Load: Low: +0.5V @ -0.2mA max. High: +2.7V @+20mA max. Output Voltage: Low: Min. 0V ; Max. 0.4V High: Min. +2.4V z Driving Capacity: Low: Max. +0.5V at 8.0mA (Sink) High: Min. 2.7V at 0.
1.4 Software Support 1.4.1 Programming Library For the customers who are writing their own programs, we provide MS-DOS Borland C/C++ programming library. ACLS-DLL2 is the Development Kit for NuDAQ ISA-Bus Cards with Analog I/O, windows 3.1/95(98)/NT. ACLS-DLL2 can be used for many programming environments, such as VC++, VB, Delphi. ACLS-DLL2 is included in the ADLINK CD. It need license. 1.4.
2 Installation This chapter describes how to install the ACL-8316/12. At first, the contents in the package and unpacking information that you should care about are described. The jumpers and switches setting for the ACL-8316/12's base address, analog input channel configuration, interrupt IRQ level, analog output configuration are also specified. 2.
After opening the card module carton, extract the system module and place it only on a grounded anti-static surface component side up. Again inspect the module for damage. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface. Note: DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED. You are now ready to install your ACL-8316/12. 2.3 ACL-8316/12's Layout Figure 2.
2.4 Jumper and DIP Switch Description You can change the ACL-8316/12's channels and the base address by setting jumpers and DIP switches on the card. The card's jumpers and switches are preset at the factory. You can change the jumper settings for your own applications. A jumper switch is closed (sometimes referred to as "shorted") with the plastic cap inserted over two pins of the jumper. A jumper is open with the plastic cap inserted over one or no pin(s) of the jumper. 2.
I/O port Address(Hex) 200-20F 1 A8 ON A9 -- 210-21F 220-22F (default) 230-23F : 300-30F : 3F0-3FF 2 A7 ON 3 A6 ON 4 A5 ON 5 A4 ON (1) (0) (0) (0) (0) (0) -- ON ON ON ON OFF (1) (0) (0) (0) (0) (1) -- ON ON ON OFF ON (1) (0) (0) (0) (1) (0) -- ON ON ON OFF OFF (1) (0) (0) (0) (1) (1) -- OFF ON ON ON ON (1) (1) (0) (0) (0) (0) -- OFF OFF OFF OFF OFF (1) (1) (1) (1) (1) (1) Table 2.1 Possible Base Address Combinations A0, ...
2.6 Analog Input Channel Configuration The ACL-8316/12 offer 16 single-ended or 8 differential analog input channels. The jumper JP7 controls the analog input channel configuration. The settings of JP7 is specified as following illustration. JP7 SING Single-ended Input (default setting) DIFF JP7 SING Differential Input DIFF Figure 2.3 Analog Input Channels Configuration 2.7 Analog Output Channel Setting 2.7.
D/A CH1 Output -10V~+10V Bipolar (Default) D/A CH1 Output 0V~10V Unipolar JP5 BI1 UP1 JP5 UP1 BI1 Figure 2.4 D/A CH1 Output Range setting D/A CH2 Output -10V~+10V Bipolar (Default) D/A CH2 Output 0V~10V Unipolar JP6 BI2 UP2 JP6 BI2 UP2 Figure 2.5 D/A CH2 Output Range setting 2.7.2 Output Mode Setting The ACL-8316/12 consists of two independently addressable latched in two ranks for each D/A converter. The first rank consists of one 12-bit input latch which can be loaded from the PC bus.
Transprant (default d tti ) JP1 Double mod B ff d JP1 D B T P D B T P Figure 2.
2.8 DMA Channel Setting The A/D data transfer of ACL-8316/12 is designed with DMA transfer capability. The setting of DMA channel 5, 6 or 7 is controlled by the jumpers JP1 and JP2. The possible settings are illustrated in the Figure 2.7 below. DMA 5 (Default) DACK JP1 7 6 5 DMA 6 DACK JP1 7 6 5 DACK JP1 DRQ JP2 7 6 5 DRQ JP2 7 6 5 DRQ JP2 DMA 7 7 6 5 7 6 5 Figure 2.7 DMA Channel Setting 2.
Figure 2.8 IRQ Level Setting 2.10 Clock Source Setting The 8254 programmable interval timer is used in the ACL-8316/12. It provides 3 independent channels of 16-bit programmable down counters. The input of counter 2 is connected to a precision 2MHz oscillator for internal pacer. The input of counter 1 is cascaded from the output of counter 2. The channel 0 is free for user's applications.
2.11 Connectors Pin Assignment The ACL-8316/12 comes equipped with two 20-pin insulation displacement connectors - CN1 and CN2 and one 37-pin D-type connector - CN3. The CN1 and CN2 are located on board and CN3 located at the rear plate. CN1 is used for digital signal output, CN2 for digital signal input, CN3 for analog input, analog output and timer/counter's signals. The pin assignment of each connector is illustrated in Figure 2.10~2.12.
z CN 3: Analog Input/Output & Counter/Timer ( for single-ended connection) CN3 AI0 AI1 AI2 AI3 AI4 AI5 AI6 AI7 A.GND A.GND V.REF +12V A.GND D.GND COUT0 ExtTrg N/C +5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 AI8 AI9 AI10 AI11 AI12 AI13 AI14 AI15 A.GND A.GND AO1 AO2 GATE0 GATE N/C ExtCLK Figure 2.12a Pin Assignment of CN3 z CN 3: Analog Input/Output & Counter/Timer ( for differential connection) CN3 AIH0 AIH1 AIH2 AIH3 AIH4 AIH5 AIH6 AIH7 A.
Legend: Ain : Analog Input Channel n ( single-ended) AIHn : Analog High Input Channel n ( differential) AILn : Analog Low Input Channel n ( differential) ExtRef n : External Reference Voltage for D/A CH n Aon : Analog Output Channel n ExtCLK : External Clock Input ExtTrig : External Trigger Signal CLK : Clock input for 8254 GATE : Gate input for 8254 COUT n : Signal output of Counter n V.ERF : Voltage Reference A.
2.12 Daughter Board Connection The ACL-8316/12 can be connected with five different daughter boards, ACLD-8125, ACLD-9137, 9182, 9185, and 9188. The functionality and connections are specified as follows. 2.12.1 Connect with ACLD-8125 The ACLD-8125 has a 37-pin D-sub connector, which can connect with ACL8316/12HG through 37-pin assemble cable. The most outstanding feature of this daughter board is a CJC ( cold junction compensation) circuit on board. 2.12.
3 Registers Format The detailed description of the ACL-8316/12‘s register format is specified in this chapter. This information is quite useful for the programmer who wish to handle the ACL-8316/12 card by low-level program. 3.1 I/O Port Address The ACL-8316 requires 16 consecutive addresses in the PC I/O address space. Table 3.1 shows the I/O address of each register with respect to the base address. The function of each register will be introduced in the following sections.
Note: The ACL-8316/12 includes both 8 bits & 16 bits I/O ports. The AD Data, DA channels, and digital I/O ports are 16 bits port. All the others are 8 bits I/O port. The 16-bit I/O data ( A/D, D/A and DIO) have to access via 16-bit I/O operation. 3.2 A/D Data Registers The value of AD data register is directly read from AD converter which address is base address + 4. The A/D data is updated whenever AD is triggered.
3.3 FIFO Enable Register The FF_ENA bit directly control FIFO memory. Clear FF_ENA bit to ‘0’ can always reset the FIFO and any read operation to the A/D FIFO port will get value ‘0’. Set FF_ENA bit to ‘1’ can enable the FIFO. Note that FF_ENA status can be read back from Base+13. Address : BASE + 8 Attribute: write only Data Format: Bit 7 6 5 4 X X X X FF_ENA: FIFO Enable Control 0: FIFO Disable 1: FIFO Enable 3.
3.5 A/D Channel Multiplexer Register The A/D channel multiplexer register is used to select the A/D channel under normal mode, or the stop channel number under the auto-scan mode. Refer to section 3.7 to find the definition of the auto-scan control bit ‘ASCAN’. When auto scanning is disabled, the register values select the AD channel number. When auto scanning is enabled, the register values set the stop channel number while the starting channel is from channel 0.
3.6 Interrupt Source Control Register The interrupt source of ACL-8316 is controlled by both of this register and the A/D mode control register. The DMAEAN bit in A/D mode control register will decide the interrupt source, too. This register values can be read back on the same port. Address : BASE + 11 Attribute: read and write Data Format: Bit 7 X 6 X 5 X 4 X 3 X 2 X 1 IS1 0 IS0 When DMAENA is set (DMA enable), interrupt must come from TC (terminal count) signal to indicate DMA transfer ending.
3.7 AD Mode Control Register The A/D mode control register is used to select A/D data transfer mode A/D trigger source, and A/D channel selection.
3.8 A/D Status Register Address : BASE + 8 Attribute: read only Data Format: Bit 7 6 5 4 3 2 1 0 AD_BUSY FF-FF FF_HF FF_EF CNH CN2 CN1 CN0 • CNH and CN2~CN0 These bits are used to feedback the channel number to be selected. When the ACL-8316/12 is set to be differential mode. CNH will be 1 always. When the A/D mode is in auto scan mode, the channel number will be increased by one automatically.
3.9 Clear Interrupt Register To read this port can generate clear interrupt signal. No matter which interrupt source is used, the clear interrupt register must be read to allow next interrupt. Address : BASE + 9 Attribute: read only Data Format: Bit 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X 3.10 Software A/D Trigger Register To read this port can generate A/D trigger signal if the AD mode control register is set to use internal software A/D trigger source.
3.12 DA Mode Control Register Address : BASE + 13 Attribute: write Data Format: Bit 7 6 5 X X X Address : BASE + 13 Attribute: read Data Format: Bit 7 X 6 X 5 X 4 X 4 X 3 X 3 FF_ENA 2 X 1 DA_FMT 2 STYP 1 DA_FMT 0 DA_MD1 0 DA_MD1 The D/A operation and D/A data format are controlled by this register and the jumper JP8. The lower two bits are programmable and can be read back too. Another two bits, the FIFO enable (FF_ENA) bit and the A/D signal type (STYP) bit, are read only.
3.13 Digital I/O register There are 16 digital input channels and 16 digital output channels are provided by the ACL-8312/16. The address Base + 14 and Base + 15 are used for both digital input and digital output control.
4 Operation Theorem The operation theorem of the functions on ACL-8316/12 card is described in this chapter. The functions include the A/D conversion, D/A conversion, digital I/O and counter/timer. The operation theorem can help you to understand how to manipulate and to program the ACL-8316/12. 4.
4.1.1 A/D Conversion Procedure For using the A/D converter, users must know about the property of the signal to be measured at first. The users can decide which channels to be used and connect the signals to the ACL-8316. Refer to the ‘Signal Connection’ (Section 2.11). In addition, users should define and control the A/D signal sources, including the A/D channel, A/D gain, and A/D signal types. Please refer to section 4.1.2. for A/D signal source control.
single-ended connection. Note that when more than two floating sources are connected, the sources must be with common ground. AIN Floating Signal Source Input Opertiona Amplifie ... To A/D V2 V1 n = 0, ..., 15 AGND Figure 4.1.1 Floating source and single-ended Differential input mode The differential input mode provides two inputs that respond to the difference signal between them.
A differential mode must be used when the signal source is differential. A differential source means the ends of the signal are not grounded. To avoid the danger of high voltage between the local ground of signal and the ground of the PC system, a shorted ground path must be connected. Figure 4.1.3 shows the connection of differential source. n = 0, ..., 8 To A/D AIHn Differentia Signal Sourc + - AILn GN Vcm = VG1 - VG2 VG1 VG2 Figure 4.1.
Signal Channel There are 16 channels in SE mode and 8 channels in DI mode. There are two ways to control the channel number. The first is the software programming and the second is the auto channel scanning, which is controlled by the ASCAN bit in AD mode control register. As ASCAN is cleared (0), the value of AD channel MUX register defines the channel to be selected. Only one channel can be selected in one moment.
4.1.3 A/D Trigger Sources Control The A/D conversion is started by trigger signal. There are total three trigger sources in the ACL-8316. One is External trigger source and two are Internal trigger sources. The trigger source is programmable by the A/D mode control register. Please refer to section 3.7 for details of the register.
4.1.4 A/D Data Buffering On the ACL-8316, the AD data will store in the A/D data register. While A/D conversion, the register keeps the previous conversion result. The data will be updated when the end of the conversion. The A/D data register can keep the newest conversion data until the ending of the next conversion. The A/D data register can store only one data and the data can be real time operated. The A/D data can also be buffered in the FIFO memory when the FIFO is enable.
4.1.5 A/D Data Transfer Modes The A/D data must be transferred to CPU for processing. On the ACL-8316, many AD data transfer modes can be used. Note that there are only two kinds of operation can transfer AD data from port into PC's memory. The data can be either read by I/O instruction (‘inport’ in terms of C language), which is handled directly by software, or transferred to memory by the DMA controller.
FIFO Half-Full Interrupt Transfer By properly programming the interrupt control register, the ACL-8316 provides FIFO half-full interrupt. As the FIFO is enable and be half-full, an interrupt is inserted and the corresponding ISR will be invoked. The ISR can read at least 512 sampling data because of the FIFO size is 1K sample. This mode can tolerate more time delay and it is interrupt driven, therefore, it is very suitable for Windows applications.
4.1.6 A/D Data Format The A/D data read either from A/D data port or the FIFO port is in the two‘s complement format. As the A/D gain is 1, the A/D signal range is roughly +10V ~ -10V bipolar. In ACL-8316, 16 bits A/D data is available. The relationship between the voltage and the value is shown in the following table: A/D Data (Hex) 7FFF 4000 0001 0000 FFFF C000 8001 8000 Decimal Value +32767 +16384 1 0 -1 -16384 -32767 -32768 Voltage (Volts) +10.00000 +5.00015 +0.00031 0.00000 -0.00031 -5.00015 -10.
where the gain is the value of the A/D gain control register. The K is a coefficient. For ACL-8316, K=32767; for ACL-8312, K=32752=2047x16.
4.2 Interrupt System The interrupt system of the ACL-8316/12 is very flexible for many applications. There are four plus one (4+1) programmable interrupt sources. The interrupt signal can be routed one of the 10 IRQ channels by jumper setting. The following diagram shows interrupt system. FIFO Half-Full Int. interrupt lines AT Bus Timer Interrupt Jumper EOC Interrupt DMA Enab le Signal Programmabl Multiplexer External Interrupt DMA Terminal Count Figure 4.
4.3 D/A Conversion The ACL-8316/12 has two unipolar analog output channels. To make the D/A output connections from the appropriate D/A output, please refer Figure 4.3. -5 or -10 INT or Ext Pin-30 ( AO0) Pin-32 ( AO1) To D/A Ref D/A + Pin-14 ( A.GND) Analog GND Figure 4.3 Connection of Analog Output Connection The operation of D/A conversion is much more simple than A/D operation.
Note that the two D/A channels could be in double buffered mode or in the transparency mode. In the transparency mode, the operation of the two D/A channels are independent. The analog out signal will real-time response the digital value written into the DACs. However, in the double buffered, the digital value of each channels is double buffered.
4.4 Digital Input and Output The ACL-8316/12 provides 16 digital input and 16 digital output channels through the connector CN1 and CN2 on board. The digital I/O signal are fully TTL/DTL compatible. The detailed digital I/O signal specification can be referred in section 1.3. 74LS244 Digital Digital Output 74LS373 From TTL Signal To TTL Devices Digital GND ACL-8112 Outside Device Figure 4.
4.5 Timer/Counter Operation The ACL-8316/12 has an 8254 programmable interval timer/counter on board. It offers 3 independent 16-bit programmable down counters; counter 1 and counter 2 are cascaded together for A/D timer pacer trigger of A/D conversion, counter 0 is free for your applications. Figure 4.5 shows the 8254 timer/counter connection.
Pacer Trigger Source The counter 1 and counter 2 are cascaded together to generate the timer pacer trigger of A/D conversion. The frequency of the pacer trigger is software controllable. The maximum pacer signal rate is 2MHz/4=500K which excess the maximum A/D conversion rate of the ACL-8316/12. The minimum signal rate is 2MHz/65535/65535, which is a very slow frequency that user may never use it. General Purpose Timer/ Counter The counter 0 is free for users' applications.
RL1 & RL0 - Select Read/Load operation ( Bit 5 & Bit 4) z RL1 0 0 1 1 RL0 0 1 0 1 OPERATION COUNTER LATCH FOR STABLE READ READ/LOAD LSB ONLY READ/LOAD MSB ONLY READ/LOAD LSB FIRST, THEN MSB M2, M1 & M0 - Select Operating Mode ( Bit 3, Bit 2, & Bit 1) z M2 0 0 x x 1 1 M1 0 0 1 1 0 0 M0 0 1 0 1 0 1 MODE 0 1 2 3 4 5 BCD - Select Binary/BCD Counting ( Bit 0) z 0 1 Note 16-BITS BINARY COUNTER BINARY CODED DECIMAL (BCD) COUNTER (4 DIGITAL) The count of the binary counter is from 0 up to 65,535 and t
5 C/C++ Library This chapter describes the DOS software library, which is free supplied. The DOS library software includes a utility program, C language library, and some demonstration programs, which can help you reduce the programming work. To program in Windows environment, please use ACLS-DLL2. The function reference manual of ACLS-DLL2 is included in the ADLINK CD. It needs license. 5.
5.2 Software Utility The ACL-8316/12‘s Utility includes System Configuration, Calibration, and Functional Testing. This utility software is designed by menu-driven based on windowing environment. Not only the text messages are shown for operating guidance, but also has the graphic to indicate you how to set right hardware configuration Running the 8316UTIL.
5.4 _8316_Initial @ Description An ACL-8316/12 card is initialized according to the card number and the corresponding base address. Every ACL-8316/12 Multi-Function Data Acquisition Card have to be initialized by this function before calling other functions. @ Syntax I16 _8316_Initial( U8 card_number,U16 base_addresss ) @ Argument card_number: the card number to be initialized, up to three cards can be initialized, the card number must be CARD_1, CARD_2 or CARD_3.
5.6 _8316_DI @ Description This function is used to read data from digital input port. There are 16-bit digital inputs on the ACL-8316/12. The digital input status can be accessed by this function directly. @ Syntax I16 _8316_DI( U16 *data ) @ Argument data: return value from digital port. @ Return Code ERR_NoError, ERR_BoardNoInit @ Example See Demo Program 'DI_DEMO.C' 5.7 _8316_DI _Channel @ Description This function is used to read data from digital input channels (bit).
5.8 _8316_DO @ Description This function is used to write data to digital output port. There are 16 digital outputs on the ACL-8316/12. You can control the digital outputs by this function directly. @ Syntax I16 _8316_DO( U16 data ) @ Argument data: value will be written to digital output port @ Return Code ERR_NoError, ERR_BoardNoInit 5.9 _8316_DO_Channel @ Description This function is used to write data to digital channel. There are 16 digital outputs on the ACL-8316/12.
5.10 _8316_DA_Set_Mode @ Description This function is used to configure the D/A output mode . There are four modes can be set when the D/A output is used. 1. DA_MODE_0: Transparency and Binary data format 2. DA_MODE_1: Transparency and Two‘s complement format 3. DA_MODE_2: double buffered and Binary data format 4.
5.11 _8316_DA @ Description This function is used to write data to D/A converters. There are two Digital-to-Analog conversion channels on the ACL-8316/12. The resolution of each channel is 12-bit; its data format can be binary or two‘s complement format. Which data format is used for this function, depends on the setting of function _8316_DA_Set_Mode(). @ Syntax I16 _8316_DA( U8 da_ch_no, I16 da_data ) @ Argument da_ch_no: D/A channel number, DA_CH_1 or DA_CH_2.
@ Argument ad_ch_no: channel number to perform AD conversion for single-ended mode: channel no. is from 0-15 for differential mode: channel no. is from 0-7 @ Return Code ERR_NoError, ERR_BoardNoInit, ERR_InvalidADChannel 5.13 _8316_AD_Range @ Description This function is used to set the A/D analog input range by means of writing data to the A/D range control register. For ACL-8316/12 card, the gain values only support 1, 2, 4, 8 four levels.
5.14 _8316_AD_Set_Mode @ Description This function is used to set the A/D trigger source, A/D channel selection and A/D data transfer mode by means of writing data to the AD Mode Control Register (refer to section 4.7). The hardware initial state of the ACL-8316/12 is set as internal software trigger with program polling data transfer. For more detailed A/D mode description, please refer to section 4.1 A/D conversion.
5.16 _8316_AD_Set_FIFO @ Description This function is used to enable the FIFO on the ACL-8312/15. As the FIFO is enabled, all A/D converted data are stored into the FIFO. The size of A/D FIFO is 1 K words on-board. @ Syntax I16 _8316_AD_Set_FIFO( Boolean flag ) @ Argument None @ Return Code ERR_NoError, ERR_BoardNoInit 5.
5.18 _8316_CLR_IRQ @ Description This function is used to clear interrupt request which requested by the ACL-8316/12. If you use interrupt to transfer A/D converted data, you should use this function to clear interrupt request status, otherwise no new coming interrupt will be generated. @ Syntax I16 _8316_CLR_IRQ( void ) @ Argument None @ Return Code ERR_NoError 5.19 _8316_AD_Soft_Trig @ Description This function is used to trigger the A/D conversion by software.
5.20 _8316_AD_Read_FIFO @ Description This function is used to get the AD conversion data which are stored in the FIFO. This function is useful when the FIFO is enabled and converted A/D data already saved in it. @ Syntax I16 _8316_AD_Read_FIFO( I16 *ad_data ) @ Argument ad_data: 16 or 12 bits A/D converted value. The data format can be referred from section 4.1.5 for details @ Return Code ERR_NoError, ERR_BoardNoInit 5.
5.22 _8316_AD_DMA_Start @ Description The function will perform A/D conversion N times with DMA data transfer by using the pacer trigger ( internal timer trigger). It will take place in the background which will not stop until the Nth conversion has completed or your program executes _8316_AD_DMA_Stop() function to stop the process. After executing this function, it is necessary to check the status of the operation by using the function _8316_AD_DMA_Status().
irq_ch_no: IRQ channel number, used to stop DMA Note: Make sure your hardware configuration is set to right IRQ interrupt level. dma_count: the number of A/D conversion ad_buf: the start address of the memory buffer to store the AD data, the buffer size must be larger than the number of AD conversion. @ Return Code ERR_NoError, ERR_BoardNoInit, ERR_InvalidADChannel, ERR_AD_InvalidGain, ERR_InvalidDMAChannel, ERR_InvalidIRQChannel, ERR_InvalidTrigSrc @ Example See Demo Program 'AD_DEMO3.C' 5.
5.24 _8316_AD_DMA_Stop @ Description This function is used to stop the DMA data transferring. After executing this function, the internal A/D trigger is disable and the A/D timer ( timer #1 and #2) is stopped. The function returns the number of the data which has been transferred, no matter if the A/D DMA data transfer is stopped by this function or by the DMA terminal count ISR. @ Syntax I16 _8316_AD_DMA_Stop( U16 *count ) @ Argument count: the number of A/D converted data which has been transferred.
@ Argument int_mode: A/D conversion by interrupt data transfer INT_MODE_0: Internal timer pacer trigger A/D conversion, EOC( end of conversion ) trigger interrupt, and get A/D converted data through I/O port. INT_MODE_1: Internal timer pacer trigger A/D conversion, FIFO_HF( FIFO half full ready ) trigger interrupt, and get 512 A/D converted data through I/O port. INT_MODE_2: External Trigger A/D conversion , and EOC( end of conversion ) trigger interrupt, and get A/D converted data through I/O port.
5.26 _8316_AD_INT_Status @ Description Since the _8316_AD_INT_Start() function is executed in background, you can issue the function _8316_AD_INT_Status to check the status of interrupt operation. @ Syntax I16 _8316_AD_INT_Status( U8 *status, U16 *count ) @ Argument status: status of the INT data transfer 0: A/D INT is completed 1: A/D INT is not completed count: current conversion count number. @ Return Code ERR_NoError, ERR_BoardNoInit @ Example See Demo Program 'AD_DEMO2.C' 5.
5.28 _8316_AD_Timer @ Description This function is used to setup the Timer #1 and Timer #2. Timer #1 & #2 are used as frequency divider for generating constant A/D sampling rate dedicatedly. It is possible to stop the pacer trigger by setting any one of the dividers as 0. Because the AD conversion rate is limited due to the conversion time of the AD converter, the highest sampling rate of the ACL-8316/12 can not exceed 100 kHz. The multiplication of the dividers must be larger than 20.
5.30 _8316_TIMER_Read @ Description This function is used to read the counter value of the Timer #0. @ Syntax I16 _8316_TIMER_Read( U16 *counter_value ) @ Argument counter_value: the counter value of the Timer #0 @ Return Code ERR_NoError, ERR_BoardNoInit @ Example See Demo Program 'TMR_DEMO.C' 5.31 _8316_TIMER_Stop @ Description This function is used to stop the timer operation. The timer is set to the 'One-shot' mode with counter value ' 0 '.
6 Calibration & Utilities In data acquisition process, how to calibrate your measurement devices to maintain its accuracy is very important. Users can calibrate the analog input and analog output channels under the users' operating environment for optimizing the accuracy. This chapter will guide you to calibrate your ACL8316/12 to an accuracy condition. 6.
6.2 VR Assignment There are five variable resistors (VR) on the ACL-8316/12 board to allow you making accurate adjustment on A/D and D/A channels. The function of each VR is specified as Table 6.1. VR1 VR2 VR3 VR4 VR5 VR6 VR7 A/D bipolar offset adjustment A/D full scale adjustment D/A channel 1 full scale adjustment D/A channel 1 offset adjustment D/A channel 2 full scale adjustment D/A channel 2 offset adjustment A/D programmable amplifier offset adjustment Table 6.1 Function of VRs 6.
6.4.2 DA Channel 2 Calibration 1. 2. 3. 4. 5. 6. Set JP6 to BI1 (Bipolar for DA Channel 2). Connect VDM (+) to CN3.AO2 pin-32 and VDM(-) to CN3.GND pin-29. Set DA2 output to 0x8000 Trim the variable resister VR6 to obtain -10.005V reading in the DVM. Set DA2 output to 0x7FF0 Trim the variable resister VR5 to obtain +10V reading in the DVM. A calibration utility is supported in the software diskette which is included in the product package.
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4. • Damage caused by leakage of battery fluid during or after change of batteries by customer/user. • Damage from improper repair by unauthorized ADLINK technicians. • Products with altered and/or damaged serial numbers are not entitled to our service. • This warranty is not transferable or extendible. • Other categories not protected under our warranty. Customers are responsible for all fees necessary to transport damaged products to ADLINK.
