User`s guide

28
•
Operation Theorem
Software Data Transfer
Usually, this mode is used with software A/D trigger mode. After the
A/D conversion is triggered by software, the software should poll the
DRDY bit until it becomes to high level. Whenever the low byte of A/D
data is read, the DRDY bit will be cleared to indicate the data is read
out.
It is possible to read A/D converted data without polling. The A/D
conversion time will not excess 8µs on ACL-8111 card. Hence, after
software trigger, the software can wait for at least 25µs then read the
A/D register without polling.
EOC Interrupt Transfer
The ACL-8111 provides hardware interrupt capability. Under this mode,
an interrupt signal is generated at end of A/D conversion (EOC) then
the data is ready to be read. It is useful to combine the interrupt
transfer with the timer pacer trigger mode. Under this mode, the data
transfer is essentially asynchronous with the control software.
When the interrupt transfer is used, you have to set the interrupt IRQ
level by hardware jumper. Please refer section 2.10 for IRQ jumper
setting. After the A/D conversion is completed, a hardware interrupt will
be inserted and its corresponding ISR (Interrupt Service Routine) will
be invoked and executed. The converted data is transferred by the ISR
program.
4.2 D/A Conversion
The operation of D/A conversion is simpler than A/D operation. You
only need to write digital values into the D/A data registers and the
corresponding voltage will be output from the AO. The ACL-8111 has
one uni-polar analog output channels. To make the D/A output
connections from the appropriate D/A output, please refer Figure 4.2.