NuDAQ® ACL-7120A Digital I/O & Timer/Counter Card User’s Guide
Copyright 1995, 2003 ADLINK TECHNOLOGY INC. All Rights Reserved. Manual Rev. 1.00: May 30, 2003 Part No: 50-11031-100 The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
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Table of Contents Chapter 1 Introduction ....................................................... 1 1.1 1.2 1.3 1.4 Features .................................................................................... 2 Applications ............................................................................... 2 Specifications ............................................................................ 3 Software Support....................................................................... 5 1.4.1 1.4.
How to Use This Guide This manual is designed to assist users in understanding the ACL-7120A and describes how to modify settings to meet specific application requirements. Chapter 1 Introduction Overview of product features, applications, and specifications. Chapter 2 Installation Describes install procedures, layout, DIP switch settings, and jumper settings. Chapter 3 Signal Connection Illustrates the connector pin assignments, timer/counter signal pad, and clock source.
1 Introduction The ACL-7120A digital I/O and counter/timer card consists of 32 digital input, 32 digital output, and 4 timer/counter channels. All digital input/output channels are TTL/DTL compatible. The most outstanding feature of the ACL7120A is that it is fully hardware and software compatible with both the ADLINK ACL-7120 and Advantech PCL-720 cards. The ACL-7120A supports additional daughter boards like the ACLD-9182 and ACLD-9185 cards.
1.1 1.
1.3 Specifications ♦ General Specification: • Dimensions: 193.5 mm x 114 mm • Bus: PC-AT bus • I/O port address: Hex 200 - Hex 3FF • Interrupt IRQ Level: IRQ3 - IRQ15 ♦ Digital Input: • Input logic low voltage: Min. -0.5V, Max. 0.8V • Input logic high voltage: Min. 2.0V, Max. 5.0V • Input loading current: Max. 0.2 mA at 0.4V • Input hysteresis: Typical 0.4V, Min. 0.2V ♦ Digital Output: • Output logic low voltage (Sink): Max. 0.5V at 24mA • Output logic high voltage (Source): Min.
• Mode: 6 programmable modes • Usable pins: • Device Usable pins ACL-7120A/3 CLK and GATE for counter 0 - counter 2 ACL-7120A/6 CLK and GATE for counter 0 - counter 3 counter usage : Device Counter usage ACL-7120A/3 Counters 0 - 2 are customizable ACL-7120A/6 Counters 0 - 2 are customizable Counter 3 is used as the event counting interrupt source or is user defined Counters 4 and 5 are cascaded for timer pacer generation • Breadboard Area: plated through hole: hole size: 1.
1.4 Software Support The ACL-7120A is programmable using simple 8-bit I/O port commands. Users can use high-level languages, such as BASIC, C, or PASCAL, or lowlevel language, such as assembly to program the board. To program under Windows or LabView, please contact an ADLINK dealer for information on the ACLS-DLL1 and ACLD-LVIEW. 1.4.1 ACLS-DLL1 The ACLS-DLL1 provides simple ACL-07120A board programming under a Windows 9x/NT/2000 environment using DLLs.
2 Installation This chapter describes how to install the ACL-7120A. Please carefully review the unpacking information before removing the product. The jumper and switch settings for the ACL-7120A base address, clock sources, interrupt IRQ level, and IRQ trigger sources are specified below. 2.
2.2 Unpacking Your ACL-7120A card contains sensitive electronic components that can be easily damaged by static electricity. Prepare a grounded anti-static mat. The operator should be wearing an antistatic wristband, grounded at the same point as the anti-static mat. Inspect the card module carton for obvious damage. Shipping and handling may cause damage to the module. Be sure there is no obvious damage due to shipping and handing by examining the shipping box.
JP2 CN5 JP1 Count 0 SW1 JP3 CN4 CN3 CN2 CN1 ACL-7120A Layout Count 1 2.3 ● ●●●●●●●●●●●●●●●●●●●●●●●●●●●●●● ● ● ●●●●●●●●●●●●●●●●●●●●●●●●●●●●●● ● ● ●●●●●●●●●●●●●●●●●●●●●●●●●●●●●● ● ● ●●●●●●●●●●●●●●●●●●●●●●●●●●●●●● ● ● ●●●●●●●●●●●●●●●●●●●●●●●●●●●●●● ● Figure 2.
2.4 Jumper and DIP Switch Description The ACL-7120A channels and base addresses can be changed through jumper settings and DIP switches on the card. The ACL-7120A is preconfigured at the factory and should not need to be changed under normal circumstances. A jumper switch is closed or "shorted" with the plastic cap inserted over two pins of the jumper. A jumper is open when the plastic cap inserted over one or no pin(s) of the jumper.
2.5 Base Address Setting The ACL-7120A requires eight consecutive address locations in the I/O address space. The base address of the ACL-7120A is restricted by the following conditions: 1. The base address must be within the range 200hex to 3FFhex. 2. The base address should not conflict with any PC I/O address. The ACL-7120A default I/O port base address 0x2A0 is set by the 6 position DIP switch SW1 (refer to Figure 2.2).
How to define the base address for the ACL-7120A? DIP1 through DIP6 in the switch SW1 are one-to-one corresponding to the PC bus address line A8 to A4. A9 is always 1 and A0~A3 are always 0. If you want to change the base address, you can only change the values of A8 to A4 (the shadowed area of the table below).
2.6 Interrupt Settings To use the interrupt function, a second counter chip (CNT 1) needs to be installed on the ACL-7120A/3. The additional CNT 1 counter chip is included with the ACL-7120A/6. The ACL-7120A offers AT bus interrupt levels (IRQ3-IRQ15), and three interrupt trigger sources (timer pacer, event, and external). The IRQ level is set by JP2 and is used to define the interrupt IRQ level. The default setting is IRQ15.
JP3 * EXT IRQ EVT IRQ TME IRQ default setting :TME IRQ Figure 2.
2.7 Clock Frequency Settings The ACL-7120A board offers 3 frequency sources: 10kHz, 100kHz, and 1 MHz. These frequencies can be double, half or quartered by placing a jumper on position " X2," "X1/2," or "X1/4," of JP1. The default setting is “X1.” X2 X1 X1/ 2 X1/ 4 * JP1 * : default setting Figure 2.
2.8 ACL-7120A Software Library Installation The DOS software library is supplied with the ACL-7120A. Function prototypes and useful constants are defined in the header files in the LIB directory. The DOS library software includes a utility program, C language libraries, and demonstration programs to help reduce the programming work. Please refer to the ACLS-DLL1 function reference manual on ADLINK CD.
3 Signal Connections 3.1 Connector Pin Assignment The ACL-7120A comes equipped with five 20-pin insulation displacement connectors CN1-CN5. CN1 and CN2 are located at the rear plate. CN3, CN4, and CN5 are located on board. Each of these connectors can be connected to flat cables of the same type. CN1 and CN3 are used for digital outputs, CN2 and CN4 are used for digital inputs, and CN5 is used for the timer/counter.
CN1: Digital OUT (0-15) DO 0 DO 2 DO 4 DO 6 DO 8 DO 10 DO 12 DO 14 GND +5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DO 1 DO 3 DO 5 DO 7 DO 9 DO 11 DO 13 DO 15 GND +12V CN 2: Digital IN (0-15) DI 0 DI 2 DI 4 DI 6 DI 8 DI 10 DI 12 DI 14 GND +5V 18 • Signal Connections 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DI 1 DI 3 DI 5 DI 7 DI 9 DI 11 DI 13 DI 15 GND STROBE0
CN 3: Digital OUT (16 - 31) DO 16 DO 18 DO 20 DO 22 DO 24 DO 26 DO 28 DO 30 GND +5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DO 17 DO 19 DO 21 DO 23 DO 25 DO 27 DO 29 DO 31 GND +12V CN 4: Digital IN (16 - 31) DI 16 DI 18 DI 20 DI 22 DI 24 DI 26 DI 28 DI 30 GND +5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DI 17 DI 19 DI 21 DI 23 DI 25 DI 27 DI 29 DI 31 GND STROBE1 Signal Connections • 19
CN 5: COUNTER CLK 2 OUT 2 GATE 2 EVENT GATE 3 GATE 4 EXT IRQ GND +5V 20 • Signal Connections 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK 1 OUT 1 GATE 1 CLK 0 OUT 0 GATE 0 GND
3.2 Timer/counter signal pads 8254 Timer/Counter CN5 Pin-8 Counter 0 CN5 Pin-12 CLK0 GATE0 CN5 Pin-2 CN5 Pin-6 CLK1 GATE1 CN5 Pin-1 CLK2 GATE2 CN5 Pin-5 OUT0 CN5 Pin-10 Counter 1 OUT1 CN5 Pin-4 Counter 2 OUT2 CN5 Pin-3 Figure 3.1 The internal timer/counter 8254 (Counter 0-Counter 2) on the ACL-7120A is configured as above (figure 3.1). Users can utilize the capabilities of the 8254 through CN5. CN5 also provides additional wiring to fully use the the 8254.
3.3 Interrupt Trigger Source The second interval timer/counter 8254 chip on the ACL-7120A is used to generate sources for interrupts. The block diagram of this chip is illustrated below (figure 3.3). Counter 3 of the 8254 is used for event counting, it will accept event signals from CN5 pin-7 and its output will trigger an interrupt when the count value of Counter 3 is becomes 0. Counters 4 and 5 are cascaded together for a timer pacer trigger interrupt. Its clock source is 4Mhz.
3.4 Clock Source Pads In addition to the clock signal pads, the frequency sources can also be wired through the soldering pads. The clock source links to the clock input of the 8254 timer/counter by soldering a wire between its corresponding pads.
3.5 Latch Digital Inputs The ACL-7120A offers a handy method to latch the input status for special applications. A latched input happens when the STROBE signal (20 pin of CN2 or CN4) is keep high. The data read from the input port will always reflect the current status. As the STROBE signal goes from High to Low, it will latch the input signal and store it in the input buffer. If STROBE is continually kept on Low, the data on input port is held as the same as the latched data.
4 Programming 4.1 I/O Registers Format The ACL-7120A occupies 16 consecutive addresses in the PC I/O address space. Table 4.
4.2 Digital I/O Programming The ACL 7120A provides 32 digital input channels and 32 digital output channels. Four I/O port address (Base+0, ..., Base+3) are reserved for these digital I/O channels.
♦ Write operation: The digital output states are written as 1 single byte to the port at address BASE+N (N=0,1,2,3). Data is written to all 8 bits as a single byte.
4.3 Programmable Interval Timer Note: The material of this section is adopted from “Intel Microprocessor and Peripheral Handbook Vol. II --Peripheral” 4.3.1 The Intel (NEC) 8254 The 8254 contains three independent, programmable, and multi-mode 16 bit counter/timers. The three independent 16 bit counters can be clocked at rates from DC to 5 MHz. Each counter can be individually programmed with 6 different operating modes by appropriately formatted control words.
Before loading or reading any of these individual counters, the control byte (Base + 7, Base + 11) must be loaded first.
4.3.3 Mode definition There are six different selectable operating modes in the 8254: Mode 0: Interrupt on terminal count The output will be initially low after the mode set operation. After the count is loaded into the selected count register, the output will remain low and the counter will begin counting. When terminal count is reached, the output will go high and remain high until the selected count register is reloaded with a mode or a new count is loaded.
Mode 3: Square Wave Rate Generator. Similar to Mode 2 except that the output will remain high until one half of the count has been completed (or for even counts) and go low for the other half of the count. This is accomplished by decrementing the counter by two on the falling edge of each clock pulse. When the counter reaches terminal count, the state of the output is changed and the counter is reloaded with the full count and the whole process is repeated.
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4. • Damage caused by leakage of battery fluid during or after change of batteries by customer/user. • Damage from technicians. • Products with altered and/or damaged serial numbers are not entitled to our service. • This warranty is not transferable or extendible. • Other categories not protected under our warranty. improper repair by unauthorized ADLINK Customers are responsible for all fees necessary to transport damaged products to ADLINK.
