User`s guide

APDCAM User’s Guide
Page 16/32
registers by writing a code into the FACTORY_RESET register. This is identical to
pressing the reset button at the camera back.
Parameter R/W
Offset
(byte)
Size
(byte)
Value
after start
Description
BOARD_VERSION R 0 1
factory
Board version code.
MC_VERSION R 1 2
factory
Microcontroller program version code.
SERIAL R 3 2
factory
Board unique serial No.
FPGA_VERSION R 5 2
factory
FPGA program version code.
STATUS1 R 8 1
N/A
Status flags, group 1
Bit 0: ADC PLL locked
Bit 1: Stream PLL locked
Bit 2-7: Reserved
STATUS2 R 9 1
N/A
Bit 0: Reserved
Bit 1: Overload
Bit 2: External clock PLL locked
Bit 3: Reserved
Bit 4-7: ADC 1-4 sample enable
CONTROL R/W 11 1
EEPROM
Various control bits:
Bit 0: External clock select
Bit 1: Clock out enable
Bit 2: External sample select
Bit 3: Sample out enable
Bit 4: Digital filter enable
Bit 5: Reserved
Bit 6: Reverse bit order in stream (1: LSB first)
Bit 7: Preamble enable
ADC_PLL_MULT R/W 12 1
EEPROM
PLL multiplier for ADC clock generation.
Valid: 20...50
ADC_PLL_DIV R/W 13 1
EEPROM
PLL divider for ADC clock generation.
Valid: 8...100
STREAM_PLL_MULT R/W 14 1
EEPROM
PLL multiplier for ADC clock generation.
Valid: 20...50
STREAM_PLL_DIV R/W 15 1
EEPROM
PLL divider for ADC clock generation.
Valid: 8...100
STREAM_CTRL R/W 16 1
0
The four lower bits enable the data output to the
four streams.
SAMPLE_NUMBER R/W 17 4
0
Requested number of samples. 0 for infinite.
CH_ENABLE R/W 21 4
EEPROM
Enable bits for the 32 channels.
RINGBUFSIZE R/W 25 2
EEPROM
Size of the ring buffer in samples per channel.
(Valid: 0...1023)
RESOLUTION R/W 27 1
EEPROM
Output resolution.
0: 14 bit, 1: 12 bit, 2: 8 bit.
SAMPLEDIV_X_7 R/W 28 2
EEPROM
Divider for generation of the sample clock from
7xADC_CLOCK. E.g. to take every second
sample write 14.
TRIGGER R/W 30 1
EEPROM
Trigger enable bits.
Bit 0: Enable external trigger rising edge.
Bit 1: Enable external trigger falling edge.
Bit 2: Enable internal trigger. (For polarity see
INT_TRIG_LEVEL
Table 5. Register table of the DAQ unit, part one.