Instruction manual

16
10 GB Communication
Version
1.0
3
& Control Card Instruction Manual
automatically switches back to internal source if the external clock frequency
(F2) is lower than 800 kHz or the External DCM is not locked.
F2 must be between 1 and 40 MHz. Use the PROGRAMEXTDCM
instruction to configure the External DCM. The lock status of the DCM and
the actual frequency of the external clock signal can be read out from the
VARIABLES ACK (FPGA Status and External Clock Frequency).
3 = 2 ×
(2. .33)
(1. .32)
The Sample Clock (F6) can be generated from the ADC Clock (F4)
divided by a programmable value (Sample Divide Value) or from external
source (F5). The Selector can be programmed by the SETCLOCKCONTROL
instruction. Sample Divide Value should be greater than one.
The ADC Clock and the Sample Clock outputs of the CONTROL and the
EIO connectors can be enabled and disabled using the SETCLOCKENABLE
instruction.