Specifications

SATA-IO Confidential 64
2.16.2. RSG-02 : Gen2 (3Gb/s) Receiver Jitter Tolerance Test
2.16.2.1. Device/Host Expected Behavior
See sections 7.2.2.6.8 and 7.3 of Serial ATA Revision 2.6. See parameter detail at beginning of RSG section.
See sections 7.4.7 and 7.4.9 of Serial ATA Revision 2.6.
Measurement Requirements
This test requirement is only applicable to products running at 3Gb/s.
The following high level procedure is used to implement the defined Receiver Tolerance test:
• Calibrate a Random Jitter (RJ) source using Mid Frequency Test Pattern (MFTP) to 0.18 UI total
o NOTE: Gen2 : 4.285 ps RMS (1 sigma for a 7 sigma 0.18 UI projection)
o The source amplitude must be calibrated to the appropriate minimum signal level outlined by Table
28 (Receiver Tolerance Testing).
 Gen2m 240mV
 Gen2i 275mV
• Add a Deterministic Jitter (DJ) source (of frequencies defined below) using a sinusoidal input on top of the
existing RJ source until a Total Jitter (TJ) amount of 0.45 UI is reached Gen2i / Gen2m.
o For consistent transmission of the Framed Long COMP pattern, it is required that 2 ALIGNs are
transmitted prior to SOF of the frame, and then subsequently every 256 Dwords.
o The source amplitude must be re-calibrated to 275mV for Gen2i or 240mV for Gen2m using the LBP
portion of the TSG-01 documented method on the COMP pattern (this must be done for each
frequency step). Following this step, it is required to confirm that the maximum differential voltage
does not exceed 750mV.
The above steps must be repeated and validated on the product under test for the frequencies listed below relative to
the DJ input source.
• 10 MHz – RSG-02a
• 33 MHz – RSG-02b
• 62 MHz – RSG-02c
• 5 MHz – RSG-02d
The methods of implementation for test equipment must provide sufficient detail for implementing the above high level
procedure using specific test equipment.
• Test is run for 20 minutes and verified to exhibit no more than zero frame errors all four frequencies above (10
MHz, 33 MHz, 62 MHz, 5 MHz). In the case where at least 1000 errors are observed during test execution,
the test iteration may stop (i.e. test time < 20 minutes for a specific frequency due to high number of errors).
Pass/Fail Criteria
2.17. Phy OOB Requirements
Min and max pulse and gap widths shall consider both the +100mV and the -100mV edges for determining starting
and ending times.
2.17.1. OOB-01 : OOB Signal Detection Threshold
2.17.1.1. Device/Host Expected Behavior
See section 7.2.2.7.1 of Serial ATA Revision 2.6.
See section 7.4.20 of Serial ATA Revision 2.6.
Measurement Requirements