Specifications

SATA-IO Confidential 63
The following parameters are to be used for creating the appropriate input source involved in the RSG tests (see
Table 31 in SATA Revision 2.6 for specification requirements):
• No SSC
• Pre-emphasis : 0dB
• No CDR (Clock Data Recover unit) to be used for the jitter calibration. Real time scopes use a dataset
derived clock, and BERTs use a 1.5 or 3 GHz square wave direct from the jitter source dependent on data
rate. More details available in MOIs.
• Rise/Fall Time : 100 ps (20/80%)
2.16.1. RSG-01 : Gen1 (1.5Gb/s) Receiver Jitter Tolerance Test
2.16.1.1. Device/Host Expected Behavior
See sections 7.2.2.6.7 and 7.3 of Serial ATA Revision 2.6.
See section 7.4.9 of Serial ATA Revision 2.6. See parameter detail at beginning of RSG section.
Measurement Requirements
This test requirement is only applicable to products running at 1.5Gb/s.
For this test, the methodology of obtaining the appropriate configuration must follow the Clock-to-Data Transmit Jitter
method outlined in section 7.2.2.3.12 in SATA Revision 2.6.
The following high level procedure is used to implement the defined Receiver Tolerance test:
• Calibrate a Random Jitter (RJ) source using Mid Frequency Test Pattern (MFTP) to 0.18 UI total
o NOTE: Gen1 : 8.57 ps RMS (1 sigma for a 7 sigma 0.18 UI projection)
o The source amplitude must be calibrated to approximately the appropriate minimum signal level
outlined by Table 28 (Receiver Tolerance Testing).
 Gen1m 240mV
 Gen1i 325mV
• Add a Deterministic Jitter (DJ) source (of frequencies defined below) using a sinusoidal input on top of the
existing RJ source using composite of minimum of 1 FRAMED COMP pattern until a Total Jitter (TJ) amount
of 0.45 UI is reached for Gen1i / Gen1m.
o For consistent transmission of the Framed Long COMP pattern, it is required that 2 ALIGNs are
transmitted prior to SOF of the frame, and then subsequently every 256 Dwords.
o The source amplitude must be re-calibrated to 325mV for Gen1i or 240mV for Gen1m using the
LBP portion of the TSG-01 documented method on the COMP pattern (this must be done for each
frequency step). Following this step, it is required to confirm that the maximum differential voltage
does not exceed 600mV.
The above steps must be repeated and validated on the product under test for the frequencies listed below relative to
the DJ input source.
• 10 MHz – RSG-01a
• 33 MHz – RSG-01b
• 62 MHz – RSG-01c
• 5 MHz – RSG-01d
The methods of implementation for test equipment must provide sufficient detail for implementing the above high level
procedure using specific test equipment.
• Test is run for 20 minutes and verified to exhibit no more than zero frame errors for all four frequencies above
(10 MHz, 33 MHz, 62 MHz, 5 MHz). In the case where at least 1000 errors are observed during test
execution, the test iteration may stop (i.e. test time < 20 minutes for a specific frequency due to high number
of errors).
Pass/Fail Criteria