Specifications

SATA-IO Confidential 56
TX+ rise
TX- fall
TSG-05a
TSG-05c
TX+ fall
TX- rise
TSG-05b
TSG-05d
• Mean R/F
bal
measured at a maximum of 20% (for products running at 3Gb/s)
Pass/Fail Criteria
• The value above shall be based on at least 10,000 UIs
2.14.6. TSG-06 : Amplitude Imbalance
2.14.6.1. Device/Host Expected Behavior
See section 7.2.2.3.10 of Serial ATA Revision 2.6.
• See section 7.4.15 of Serial ATA Revision 2.6.
Measurement Requirements
• This test requirement is only applicable to products running at 3Gb/s.
• Due to characteristics of the MFTP, it is required the measurement points be taken at 0.5UI of the 2
nd
bit
within the pattern. All amplitude values for this measurement shall be the statistical mode measured at 0.5 UI
nominal over a minimum of 10,000 UI.
• The amplitude imbalance (Amp
bal
) for each UI shall be computed using the following formula (directly from
Sec 7.4.15 of Serial ATA Revision 2.6):
o ABS(TX+ amplitude – TX- amplitude) / ((TX+ amplitude + TX- amplitude)/2)
• Results for HFTP [TSG-06a] and MFTP [TSG-06b] shall be captured.
• The Amp
bal
shall not exceed a maximum of 10% (for products running at 3Gb/s)
Pass/Fail Criteria
2.14.7. TSG-07 : Gen1 (1.5Gb/s) TJ at Connector, Clock to Data, f
BAUD
/10 (Obsolete)
2.14.7.1. Device/Host Expected Behavior
See sections 7.2.2.3.11 and 7.3 of Serial ATA Revision 2.6.
This test is informative for all products.
• See section 7.4.8 of Serial ATA Revision 2.6.
Measurement Requirements
• For products which support 3Gb/s, this requirement would be tested at 1.5Gb/s.
• The loop damping factor for the reference PLLs is required to be 0.707.
• There are several different patterns defined within the specification and are intended to be used to verify this
requirement. In order to ensure efficient test time of products within the Interoperability Testing, testing of this
requirement will be limited to the following patterns as defined in the SATA Revision 2.6 specification: High
Frequency Test Pattern (HFTP) [TSG-07a], and Lone Bit Pattern (LBP) [TSG-07b]. It is optional to
additionally test using the Simultaneous Switching Outputs Pattern (SSOP) [TSG-07c] as a third pattern.
• For this test, the methodology of obtaining the result must follow the Clock-to-Data Transmit Jitter method
outlined in section 7.2.2.3.12 in SATA Revision 2.6, similar to that for obtaining 3Gb/s results for TSG-11 and