Datasheet

Function Pulse counter
The Pulse counter is an interface for the acquisition of external digital
pulses. Each rising or falling edge on the counter input starts decrementing
from the initially set counter value. An interrupt is generated at logical “0”,
i.e. the digital output is set or reset.
4 x 32-bit downward counters
•
Optical isolation of the inputs and outputs through opto-couplers to •
prevent ground loops
Each counter can be loaded with a predened counter value
•
Interrupt at overow•
Output can be set or reset at overow•
Polarity of the inputs selectable through software •
The interface includes:
4 x 32-bit counters•
4 independent 32-bit registers, readable through the data bus•
a function and control logic.•
Used signals
Pin name Signal type Function
Ax +/- Diff./TTL/24 V* Input of the 1st counter
Bx +/- Diff./TTL/24 V* Input of the 2nd counter
Cx +/- Diff./TTL/24 V* Input of the 3rd counter
Dx +/- Diff./TTL/24 V* Input of the 4th counter
H 24 V/5 V optional Common digital output of the counter
x: Number of the function module (see pin assignment page 179)
* 24 V for the APCI-1710-24V
Function PWM (Pulse width modulation)
The function PWM is an interface for pulse width modulation.
It generates a frequency and denes the time duration (pulse width) of the
“Low” and “High” level. The function generates rectangle signals.
The output pulses from the timer generate the pulse width modulation.
PWM generator
The “Low/High” time-divider factor is written in the timer and determines
the output frequency. The input frequency is set according to the PCI clock
or the 40 MHz quartz of the board.
The function includes:
a 32-bit frequency generator for setting the “Low” and “High” levels
•
2 digital inputs as start or stop trigger•
2 digital frequency outputs•
Properties
Optical isolation of the inputs and outputs through opto-couplers to •
prevent ground loops
Interrupt status at the end of a period
•
Selection of the start level•
Selection of the stop level•
Hardware gate•
Software gate•
Typical applications
Frequency generation•
Pulse width modulation•
Drive technology•
Block diagram PWM
Ax/Bx Signal
OUT
GATE
CLK
Timer
Reload
Gate
CLK Selection
PCI Clock / 4
10 MHz
Low Timing
High Timing
Block diagram Pulse counter
Used signals
Signal name Pin name Signal type Function
PWM_OUT_Ch0_x Ax +/- Diff./TTL output digital output PWM 0
PWM_OUT_Ch1_x Bx +/- Diff./TTL output digital output PWM 1
GATE_Ch0_x Cx +/- Diff./TTL input Gate input PWM 0
GATE_Ch1_x Dx+/- Diff./TTL input Gate input PWM 1
DIG_IN_E_x Ex 24 V input digital input
DIG_IN_F_x Fx 24 V input digital input
DIG_IN_G_x Gx 24 V input digital input
DIG_OUT_H_x Hx 24 V output digital output PWM 0
or freely controllable
x: Number of the function module (See pin assignment page 179)
The PWM function only can be used restricted to the 24 V version. Only PWM0 is available for
the DIG_OUT_H_x 24 V output.
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184
PCI, counter – APCI-1710