Technical Manual
Table Of Contents
- Wireless Sensor Interface A720 (addIT™)
- 1. About the A720
- 2. Hardware
- 4. Software
- 4.1. AMOS
- 4.2. Mode Check
- 4.3. A/D Task
- 4.4. The Terminal Task
- 4.5. The Radio Interface Task
- 4.5.1. Digital Squelch
- 4.5.2. Modulation Technique Used
- 4.5.3. Generic Format of a Radio Frame
- 4.5.4. Data Frames
- 4.5.5. Frame Types
- 4.5.5.1. Request
- 4.5.5.2. Broadcast Answer
- 4.5.5.3. Set I/O Request
- 4.5.5.4. Read I/O Answer
- 4.5.5.5. Broadcast Request
- 4.5.5.6. Ping
- 4.5.5.7. Pong
- 4.5.5.8. Memory Dump Request
- 4.5.5.9. Memory Dump Answer
- 4.5.5.10. Data
- 4.5.5.11. Set ID
- 4.5.5.12. Set Slot Time and Sample Rate
- 4.5.5.13. Set Frequency
- 4.5.5.14. Set Battery Charge Levels
- 4.5.5.15. Set Pulse Counters Parameters
- 4.5.5.16. General Acknowledge
8
Wireless Sensor Interface A720 (addIT™)
chip, a third-overtone quartz oscillator oscillating on 44.545 MHz. The 12.5/25 kHz
selectivity is obtained through the use of the two ceramic filters CF1 and CF2 (ver-
sion GX for 12.5 kHz or EX for 25 kHz channel spacing), exhibiting a low group delay
time. An interesting feature of U10 is its coilless demodulator, which is PLL based.
By adjusting R67 and R60 one can change the bandwidth and the central frequency
of the IF demodulator.
The data signal is obtained on pin 17 of U10 and is buffered by means of U8:D. In
addition to the data signal, an RSSI signal is obtained on the pin 18 of the same U10.
The signal is multiplexed with other DC signals (battery level and on-board temper-
ature) by means of U6 and U7 and then is presented to one of the A/D inputs of the
microcontroller.
The entire receiver section is enabled by the microcontroller through Q8.
2.1.2. Synthesizer Section
The synthesizer is based on a very low power PLL chip, U2. An important feature of
the chip is its FastLock™ mechanism, which improves the locking speed of the loop
without compromising on the VCO noise. The operation of the PLL chip is directed
by the microcontroller (operating frequency and channel step) and are therefore fully
under software control. The frequency reference is obtained from the highly stable
temperature compensated crystal oscillator OSC1.
There are two separated VCOs: one for the receiver section and a second for the
transmitter section. The receiver oscillator is 45 MHz higher than the transmitter os-
cillator, the latter being on the programmed operating frequency. This solution opti-
mizes the operating range of the individual VCOs, and keeps the noise level down.
The receiver VCO is realized with Q6 as oscillator and Q4 as buffer/amplifier, while
the transmitter VCO with the pair Q2/Q1. The configuration of the two VCOs is very
similar: in order to minimize the power consumption, the transistors are connected
in series from a DC perspective, the buffer being the load of the oscillator.
A small amount of RF from each VCO is fed to the PLL chip input (to the internal
prescaler) by means of the group C47/R27, and C16/R7 respectively. The output of
the PLL from the phase comparator/charge pump is filtered by means of the low
pass filter formed by C35/R29/C36/R22/C55 and applied to the two varicap diodes
D4 and D3. In addition, the FastLock mechanism occasionally activates R21 to in-
crease the current of the charge pump (you may want to consult National Semicon-
ductor’s Application Note AN-1000 “A Fast Locking Scheme for PLL Frequency
Synthesizers”, by D. Byrd, C. Davis, W.O. Keese, July 1995 for additional details on
the FastLock mechanism).