Datasheet

DocID8349 Rev 7 89/170
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals
169
1: A Counter 2 overflow has occurred.
Lite timer autoreload register (LTARR)
Read / Write
Reset Value: 0000 0000 (00h)
• Bits 7:0 = AR[7:0] Counter 2 Reload Value
These bits register is read/write by software. The LTARR value is automatically loaded
into Counter 2 (LTCNTR) when an overflow occurs.
Lite timer counter 2 (LTCNTR)
Read only
Reset Value: 0000 0000 (00h)
• Bits 7:0 = CNT[7:0] Counter 2 Reload Value
This register is read by software. The LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
Lite timer control/status register (LTCSR1)
Read / Write
Reset Value: 0x00 0000 (x0h)
• Bit 7 = ICIE Interrupt Enable
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
• Bit 6 = ICF Input Capture Flag
This bit is set by hardware and cleared by software by reading the LTICR register.
Writing to this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialise the ICF bit by reading the LTICR register
• Bit 5 = TB Timebase period selection
This bit is set and cleared by software.
7 0
AR7 AR7 AR7 AR7 AR3 AR2 AR1 AR0
7 0
CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0
7 0
ICIE ICF TB TB1IE TB1F −−−