Datasheet

On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
88/170 DocID8349 Rev 7
11.3.4 Low power modes
11.3.5 Interrupts
Note: The TBxF and ICF interrupt events are connected to separate interrupt vectors (see
Interrupts chapter).
They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the
interrupt mask in the CC register is reset (RIM instruction).
11.3.6 Register description
Lite timer control/status register 2 (LTCSR2)
Read / Write
Reset Value: 0000 0000 (00h)
• Bits 7:2 = Reserved, must be kept cleared.
• Bit 1 = TB2IE Timebase 2 Interrupt enable
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
• Bit 0 = TB2F Timebase 2 Interrupt Flag
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
0: No Counter 2 overflow
Table 37. Effect of low power modes on Lite timer
Mode Description
SLOW
No effect on Lite timer
(this peripheral is driven directly by f
OSC
/32)
WAIT No effect on Lite timer
ACTIVE-HALT No effect on Lite timer
HALT Lite timer stops counting
Table 38. TBxF and ICF interrupt events
Interrupt event Event flag
Enable Control
bit
Exit from
WAIT
Exit from
ACTIVE-
HALT
Exit from
HALT
Timebase 1 event TB1F TB1IE Yes Yes No
Timebase 2 event TB2F TB2IE Yes No No
IC event ICF ICIE Yes No No
7 0
000000TB2IETB2F