Datasheet

On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
84/170 DocID8349 Rev 7
Input capture register high (ATICRH)
Read only
Reset Value: 0000 0000 (00h)
Input capture register low (ATICRL)
Read only
Reset Value: 0000 0000 (00h)
• Bits 15:12 = Reserved.
• Bits 11:0 = ICR[11:0] Input capture data.
This is a 12-bit register which is readable by software and cleared by hardware after a
reset. The ATICR register contains captured the value of the 12-bit CNTR register
when a rising or falling edge occurs on the ATIC pin. Capture will only be performed
when the ICF flag is cleared.
Transfer control register (TRANCR)
Read/Write
Reset Value: 0000 0001 (01h)
• Bits 7:1 Reserved. Forced by hardware to 0.
• Bit 0 = TRAN Transfer enable
This bit is read/write by software, cleared by hardware after each completed transfer
and set by hardware after reset.
It allows the value of the DCRx registers to be transferred to the DCRx shadow
registers after the next overflow event.
The OPx bits are transferred to the shadow OPx bits in the same way.
15 8
0 0 0 0 ICR11 ICR10 ICR9 ICR8
7 0
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
7 0
0000000TRAN
Table 36. Register map and reset values
Address
(Hex.)
Register
label
7654 3 2 10
0D
ATCSR
Reset value
0
ICF
0
ICIE
0
CK1
0
CK0
0
OVF
0
OVFIE
0
CMPIE
0
0E
CNTRH
Reset value
0000
CNTR11
0
CNTR10
0
CNTR9
0
CNTR8
0