Datasheet

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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals
169
Break control register (BREAKCR)
Read/Write
Reset Value: 0000 0000 (00h)
• Bits 7:6 = Reserved. Forced by hardware to 0.
• Bit 5 = BA Break Active
This bit is read/write by software, cleared by hardware after reset and set by hardware
when the BREAK pin is low. It activates/deactivates the Break function.
0: Break not active
1: Break active
• Bit 4 = BPEN Break pin enable
This bit is read/write by software and cleared by hardware after Reset.
0: Break pin disabled
1: Break pin enabled
• Bits 3:0 = PWM[3:0] Break pattern
These bits are read/write by software and cleared by hardware after a reset. They are
used to force the four PWMx output signals into a stable state when the Break function
is active.
PWMx duty cycle register high (DCRxH)
Read / Write
Reset Value: 0000 0000 (00h)
PWMx duty cycle register low (DCRxL)
Read / Write
Reset value: 0000 0000 (00h)
• Bits 15:12 = Reserved
• Bits 11:0 = DCR[11:0] PWMx duty cycle value
This 12-bit value is written by software. It defines the duty cycle of the corresponding
PWM output signal (see Figure 36).
In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle
of the PWMx output signal (see Figure 36). In Output Compare mode, they define the
value to be compared with the 12-bit upcounter value.
7 0
0 0 BA BPEN PWM3 PWM2 PWM1 PWM0
15 8
0 0 0 0 DCR11 DCR10 DCR9 DCR8
7 0
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0