Datasheet

On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2

74/170 DocID8349 Rev 7

11.1.6 Register description

Control register (CR)

Read / Write

Reset value: 0111 1111 (7F h)

• Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by hardware after a reset.

When WDGA = 1, the watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

• Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset is produced when it rolls over from

40h to 3Fh (T6 becomes cleared).

11.2 12-bit autoreload timer 2 (AT2)

11.2.1 Introduction

The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based

on a free-running 12-bit upcounter with an input capture register and four PWM output

channels. There are 6 external pins:

– Four PWM outputs

– ATIC pin for the Input Capture function

– BREAK pin for forcing a break condition on the PWM outputs.

7 0

WDGA T6 T5 T4 T3 T2 T1 T0

Table 32. Watchdog timer register map and reset values

Address

(Hex.)

label

76543210

002Eh

WDGCR

Reset value

WDGA