Datasheet

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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 I/O ports
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Figure 32. Interrupt I/O port state transitions
10.4 Unused I/O pins
Unused I/O pins must be connected to fixed voltage levels. Refer to Section 13.8: I/O port
pin characteristics.
10.5 Low power modes
10.6 Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM
instruction).
10.7 Device-specific I/O port configuration
The I/O port register configurations are summarized as follows:
Standard ports
01
floating/pull-up
interrupt
INPUT
00
floating
(reset state)
INPUT
10
open-drain
OUTPUT
11
push-pull
OUTPUT
XX
= DDR, OR
Table 24. Effect of low power modes on I/O ports
Mode Description
WAIT No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.
HALT No effect on I/O ports. External interrupts cause the device to exit from HALT mode.
Table 25. I/O port interrupt control/wake-up capability
Interrupt event Event flag
Enable
control bit
Exit from
WAIT
Exit from
HALT
External interrupt on selected
external event
-
DDRx
ORx
Yes Yes
Table 26. Ports PA7:0, PB6:0
Mode DDR OR
Floating input 0 0
Pull-up input 0 1