Datasheet

DocID8349 Rev 7 67/170
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 I/O ports
169
Note: Refer to the Section 10.7: Device-specific I/O port configuration for device specific
information.
Table 22. I/O port mode options
(1)
1. Legend:
NI - not implemented
Off - implemented not activated
On - implemented and activated.
Configuration mode Pull-up P-buffer
Diodes
to V
DD
to V
SS
Input
Floating with/without interrupt Off
Off
On
On
Pull-up with/without interrupt On
Output
Push-pull
Off
On
Open drain (logic level) Off
True open drain NI NI NI
(2)
2. The diode to V
DD
is not implemented in the true open drain pads. A local protection between the pad and
V
OL
is implemented to protect the device against positive stress.
Table 23. I/O configurations
I/O port Hardware configuration
Input
(1)
NOTE 3
condition
Pad
V
DD
R
PU
External interrupt
Polarity
Databus
Pull-up
Interrupt
DR register access
W
R
From
other
pins
source (ei
x
)
selection
DR
register
condition
Alternate input
Analog input
To on-chip peripheral
Combinational
logic