Datasheet

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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Power saving modes
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Figure 29. AWUF halt timing diagram
Figure 30. AWUF mode flowchart
1. WDGHALT is an option bit (see Section 15.1: Option bytes for more details).
2. Peripheral clocked with an external clock source can still be active.
3. Only an AWUF interrupt and some specific interrupts can exit the MCU from HALT mode (such as external
AWUF interrupt
f
CPU
Run mode HALT mode 256 or 4096 t
CPU
Run mode
f
AWU_RC
Clear
by software
t
AWU
Reset
Interrupt
(3)
Y
N
N
Y
CPU
Main osc
Peripherals
(2)
I[1:0] bits
OFF
OFF
10
OFF
Fetch RESET vector
or service interrupt
CPU
Main osc
Peripherals
I[1:0] bits
ON
OFF
XX
(4)
ON
CPU
Main osc
Peripherals
I[1:0] bits
ON
ON
XX
(4)
ON
256 or 4096 CPU clock
delay
(5)
Watchdog
ENABLE
DISABLE
WDGHALT
(1)
0
Watchdog
reset
1
cycle
AWU RC osc ON
AWU RC osc OFF
AWU RC osc OFF
HALT instruction
(Active-halt disabled)
(AWUCSR.AWUEN=1)