Datasheet

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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Power saving modes
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Note: As soon as ACTIVE-HALT is enabled, executing a HALT instruction while the Watchdog is
active does not generate a
RESET.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Figure 26. ACTIVE-HALT timing overview
1. This delay occurs only if the MCU exits ACTIVE-HALT mode by means of a RESET.
Figure 27. ACTIVE-HALT mode Flow-chart
1. Peripherals clocked with an external clock source can still be active.
2. Only the RTC1 interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode. Refer to
Table 12: Interrupt mapping for more details.
3. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
haltRun Run
256 or 4096 CPU
cycle delay
(1)
Reset
or
interrupt
HALT
instruction
Fetch
vector
Active-
[ACTIVE-HALT enabled]
HALT instruction
Reset
Interrupt
(2)
Y
N
N
Y
CPU
Oscillator
Peripherals
(1)
Ibit
ON
OFF
0
OFF
Fetch reset vector
or service interrupt
CPU
Oscillator
Peripherals
(1)
Ibit
ON
OFF
X
(3)
ON
CPU
Oscillator
Peripherals
Ibit
ON
ON
X
(3)
ON
256 or 4096 CPU clock
delay
(ACTIVE-HALT enabled)
(AWUCSR.AWUEN=0)
cycle