Datasheet

Power saving modes ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
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ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with HALT mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog RESET (see Section 15.1: Option bytes for
more details).
Figure 24. HALT timing overview
HALTRun Run
256 or 4096 CPU
cycle delay
Reset
or
interrupt
HALT
instruction
Fetch
vector
[ACTIVE-HALT disabled]