Datasheet

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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Power saving modes
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Figure 23. WAIT mode flowchart
1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
9.4 HALT mode
The HALT mode is the lowest power consumption mode of the MCU. It is entered by
executing the "HALT” instruction when ACTIVVE-HALT is disabled (see Section 9.5:
ACTIVE-HALT mode for more details) and when the AWUEN bit in the AWUCSR register is
cleared.
The MCU can exit HALT mode on reception of either a specific interrupt (see Table 12:
Interrupt mapping) or a reset. When exiting HALT mode by means of a reset or an interrupt,
the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to
stabilize the oscillator. After the startup delay, the CPU resumes operation by servicing the
interrupt or by fetching the reset vector which woke it up (see Figure 25: HALT mode
flowchart).
When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In HALT mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
WFI INSTRUCTION
RESET
INTERRUPT
Y
N
N
Y
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
ON
0
OFF
Fetch reset vector
or service interrupt
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
OFF
0
ON
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
ON
X
(1)
ON
cycle delay
256 or 4096 CPU clock