Datasheet

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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Supply, reset and clock management

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7.6.4 Register description

System integrity (SI) control/status register (SICSR)

Read / Write

Reset Value: 0000 0xx0 (0xh)

• Bit 7:5 = Reserved, must be kept cleared.

• Bit 4 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generated by the Watchdog peripheral. It is

set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD

Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).

Combined with the LVDRF flag information, the flag description is given by the

following table:

• Bit 3 = LOCKED PLL Locked Flag

This bit is set and cleared by hardware. It is set automatically when the PLL reaches its

operating frequency.

0: PLL not locked

1: PLL locked

• Bit 2 = LVDRF LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by

hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled

by OPTION BYTE, the LVDRF bit value is undefined.

• Bit 1 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt

request is generated when the AVDF bit is set.

0: V

over AVD threshold

1: V

under AVD threshold

Note: Refer to Monitoring the VDD main supply on page 43 and to Figure 19: Using the AVD to

monitor VDD for additional details.

• Bit 0 = AVDIE Voltage detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated when the

AVDF flag is set. The pending interrupt information is automatically cleared when

software enters the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

7 0

0 0 0 WDGRF LOCKED LVDRF AVDF AVDIE

Table 11. Flag description

RESET sources LVDRF WDGRF

External RESET

pin 0 0

Watchdog 0 1

LVD 1 X